Launch HDL Simulator for Use with MATLAB Component Session :: HDL Cosimulation Using MATLAB Component Function (HDL Verifier™ User's Guide)

• Getting Started

• User's Guide

• HDL Verification with Cosimulation

• HDL Cosimulation Using MATLAB Test Bench Function

• HDL Cosimulation Using MATLAB Component Function

Using a MATLAB Function as a Component

Create a MATLAB Component Function for Use with the HDL Simulator

• Code HDL Modules for Visualization Using MATLAB

• Create an HDL Verifier MATLAB Component Function

• Place Component Function on MATLAB Search Path

• Start Connection to HDL Simulator for Component Function Session

• Launch HDL Simulator for Use with MATLAB Component Session

Launching the HDL Simulator for Component Session

Loading an HDL Design for Visualization

• Invoke matlabcp to Bind MATLAB Component Function Calls

Invoking the MATLAB Component Function Command matlabcp

Binding the HDL Module Component to the MATLAB Component Function

• Schedule Options for a Component Session

About Scheduling Options for Component Sessions

Scheduling Component Session Using matlabcp Arguments

Scheduling Component Functions Using the tnext Parameter

• Run MATLAB Component Function Simulation

Process for Running MATLAB Component Function Cosimulation

Checking the MATLAB Server's Link Status for Component Cosimulation

Running a Component Function Cosimulation

Applying Stimuli to Component Function with the HDL Simulator force Command

Restarting a Component Simulation

Stop Component Simulation

• HDL Cosimulation Using MATLAB System Object

Verifying Viterbi Decoder Using MATLAB System Object and Mentor Graphics ModelSim

• Simulating an HDL Component in a Simulink Test Bench Environment

Understanding How the HDL Simulator and Simulink Software Communicate Using HDL Verifier For Test Bench Simulation

HDL Cosimulation Block Features for Test Bench Simulation

Creating Your Simulink Model

Running Test Bench Hardware Model in Simulink

Adding a Value Change Dump (VCD) File (Optional)

Overview to Coding HDL Components for Simulink Test Bench Sessions

Specifying Port Direction Modes in the HDL Component for Test Bench Use

Specifying Port Data Types in the HDL Component for Test Bench Use

Compiling and Elaborating the HDL Design for Test Bench Use

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Test Bench Cosimulation

Insert HDL Cosimulation Block

Connect Block Ports

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Test Bench Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Test Bench Cosimulation and the HDL Verifier HDL Cosimulation Block

Tutorial Overview

Developing the VHDL Code

Compiling the VHDL File

Creating the Simulink Model

Setting Up ModelSim for Use with Simulink

Loading Instances of the VHDL Entity for Cosimulation with Simulink

Running the Simulation

Shutting Down the Simulation

• Replacing an HDL Component with a Simulink Algorithm

Understanding How the HDL Simulator and Simulink Software Communicate Using HDL Verifier For Component Simulation

HDL Cosimulation Block Features for Component Simulation

Overview to Coding HDL Modules for Simulink Component Simulation

Specifying Port Direction Modes in the HDL Module for Component Simulation

Specifying Port Data Types in the HDL Module for Component Simulation

Compiling and Elaborating the HDL Design for Component Simulation

Creating the Simulink Model for Component Cosimulation

Running and Testing a Component Hardware Model in Simulink

Adding a Value Change Dump (VCD) File to Component Model (Optional)

Starting the HDL Simulator from MATLAB

Loading an Instance of an HDL Module for Component Cosimulation

Insert HDL Cosimulation Block

Connect Block Ports

Accessing the HDL Cosimulation Block Interface

Mapping HDL Signals to Block Ports

Specifying the Signal Data Types

Configuring the Simulink and HDL Simulator Timing Relationship

Configuring the Communication Link in the HDL Cosimulation Block

Specifying Pre- and Post-Simulation Tcl Commands with HDL Cosimulation Block Parameters Dialog Box

Programmatically Controlling the Block Parameters

Setting Simulink Software Configuration Parameters

Determining an Available Socket Port Number

Checking the Connection Status

Running and Testing a Component Cosimulation Model

Avoiding Race Conditions in HDL Simulation with Component Cosimulation and the HDL Verifier HDL Cosimulation Block

• Recording Simulink Signal State Transitions for Post-Processing

Introduction to the To VCD File Block

Using the To VCD File Block

Tutorial: Overview

Tutorial: Instructions

• HDL Cosimulation Wizard

Description

Workflow for Using the Cosimulation Wizard to Create Test Bench or Component Function

Workflow for Using the Cosimulation Wizard to Create a MATLAB System Object

Workflow for Using the Cosimulation Wizard to Create a Simulink Block

Common Workflows

MATLAB Workflow

MATLAB System Object Workflow

Simulink Workflow

Cosimulation Wizard for MATLAB System Object

Verify Raised Cosine Filter Design With Generated MATLAB Component

Verify Raised Cosine Filter Design With Generated Simulink Test Bench

• HDL Cosimulation Reference

Machine Configuration Requirements

HDL Simulator Startup

HDL Verifier Libraries

Setup Diagnostics and Customization

Adding Questa ADMS Support

Cross-Network Cosimulation

Writing Functions Using the HDL Instance Object

Writing Functions Using Port Information

Applying Direct Feedthrough to Eliminate Block Simulation Latency

Obtaining Baseline Performance Numbers

Analyzing Simulation Performance

Cosimulating Frame-Based Signals with Simulink

Overview to Avoiding Race Conditions

Potential Race Conditions in Simulink Cosimulation Sessions

Potential Race Conditions in MATLAB Cosimulation Sessions

Search MATLAB Documentation
R2012a Documentation → HDL Verifier
View documentation for other releases	Learn more about HDL Verifier

Launch HDL Simulator for Use with MATLAB Component Session

Launching the HDL Simulator for Component Session

Loading an HDL Design for Visualization

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