Overview of Component Features

The TLM generator exports a target TLM component from a Simulink model subsystem. The target TLM component has a single TLM socket that supports read and write transactions using the TLM generic protocol and generic payload.

The following diagram illustrates the simplest behavior you can specify for the generated TLM component. It contains no memory map or command and status register and executes transactions immediately.

There are a number of options you can use to control the architecture of the generated TLM component. Incorporating a memory map is one of the most effective options. The following figure demonstrates the behavior of a generated TLM component with a full complement of features enabled.

You can set options for the following TLM component features:

• Memory Mapping

  • No memory map

  • Automatically generated memory map with single address

  • Automatically generated memory map with individual addresses

• Command and Status Register

• Interrupt

• Test and Set Register

• Algorithm Execution

• Register and Buffering

• Temporal Decoupling

• TLM Component Timing Values

• TLM Component Naming and Packaging

TLM Component Architecture

Memory Mapping

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