Product Overview

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Automated HDL Code Generation Expected Users Key Features and Components

Automated HDL Code Generation

Hardware description language (HDL) code generation accelerates the development of application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs and bridges the gap between system-level design and hardware development.

Traditionally, system designers and hardware developers use HDLs, such as very high speed integrated circuit (VHSIC) hardware description language (VHDL) and Verilog, to develop hardware designs. Although HDLs provide a proven method for hardware design, the task of coding filter designs, and hardware designs in general, is labor intensive and the use of these languages for algorithm and system-level design is not optimal. Users of the Filter Design HDL Coder™ product can spend more time on fine-tuning algorithms and models through rapid prototyping and experimentation and less time on HDL coding. Architects and designers can efficiently design, analyze, simulate, and transfer system designs to hardware developers.

In a typical use scenario, an architect or designer uses DSP System Toolbox™ GUIs (FDATool or filterbuilder) to design a filter. Then, a designer uses the Filter Design HDL Coder GUI or command-line interface to configure code generation options and generate a VHDL or Verilog implementation of the design and a corresponding test bench. The generated code adheres to a clean HDL coding style that enables architects and designers to quickly address customizations. The test bench feature increases confidence in the correctness of the generated code and saves potential time spent on test bench implementation.

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Expected Users

The Filter Design HDL Coder software is a tool for system and hardware architects and designers who develop, optimize, and verify hardware signal filters. These designers are experienced with VHDL or Verilog, but can benefit greatly from a tool that automates HDL code generation. The Filter Design HDL Coder interface provides designers with efficient means for creating test signals and test benches that verify algorithms, validating models against standard reference designs, and translate legacy HDL descriptions into system-level views.

Users are expected to have prerequisite knowledge in the following subject areas:

• Hardware design and system integration

• VHDL or Verilog

• HDL simulators

Users are also expected to have experience with the following products:

• MATLAB^®

• DSP System Toolbox

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Key Features and Components

Key features of the Filter Design HDL Coder software include the following:

• Graphical user interface (GUI) accessible from Filter Design and Analysis Tool (FDATool), filterbuilder, or MATLAB command line

• MATLAB command-line interface

• Support for the following discrete-time filter structures:

  • Finite impulse response (FIR)

  • Antisymmetric FIR

  • Transposed FIR

  • Symmetric FIR

  • Second-order section (SOS) infinite impulse response (IIR) Direct Form I

  • SOS IIR Direct Form I transposed

  • SOS IIR Direct Form II

  • SOS IIR Direct Form II transposed

  • Discrete-Time Scalar

  • Delay filter

  • Farrow (fractional delay) filter

• Support for the following multirate filter structures:

  • Cascaded Integrator Comb (CIC) interpolation

  • Cascaded Integrator Comb (CIC) decimation

  • Direct-Form Transposed FIR Polyphase Decimator

  • Direct-Form FIR Polyphase Interpolator

  • Direct-Form FIR Polyphase Decimator

  • FIR Hold Interpolator

  • FIR Linear Interpolator

  • Direct-Form FIR Polyphase Sample Rate Converter

  • Farrow sample rate converter

• Support for cascade filters (multirate and discrete-time)

• Generation of code that adheres to a clean HDL coding style

• Options for optimizing numeric results of generated HDL code

• Options for specifying parallel, serial (fully, partly or cascade), or distributed arithmetic architectures for filter realizations

• Options for controlling the contents and style of the generated HDL code and test bench

• Test bench generation for validating the generated HDL filter code

• Test bench optionally partitioned into code, data, and helper function files

• Complex coefficients and complex input signals supported for fully parallel FIR, CIC, and some other filter structures

• Support for programmable coefficients for FIR and IIR filter coefficients

• VHDL and Verilog test bench options

• Automatic generation of scripts for third-party simulation and synthesis tools

• Automatic generation of a script that captures all non-default GUI settings for HDL code and test bench generation

• Automatic generation of HDL Cosimulation blocks for use with third-party HDL simulators

• Automatic generation of a Simulink^® model that is configured for both Simulink simulation of your filter design, and cosimulation of your design with an HDL simulator

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Getting Started

Installation

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