| ClockProcessPostfix | Specify string to append to HDL clock process names |
| CoeffPrefix | Specify prefix (string) for filter coefficient names |
| ComplexImagPostfix | Specify string to append to imaginary part of complex
signal names |
| ComplexRealPostfix | Specify string to append to real part of complex signal
names |
| EntityConflictPostfix | Specify string to append to duplicate VHDL entity or Verilog
module names |
| InstancePrefix | Specify string prefixed to generated component instance
names |
| PackagePostfix | Specify string to append to specified filter name to form
name of VHDL package file |
| ReservedWordPostfix | Specify string to append to value names, postfix values,
or labels that are VHDL or Verilog reserved words |
| SplitArchFilePostfix | Specify string to append to specified name to form name
of file containing filter's VHDL architecture |
| SplitEntityArch | Specify whether generated VHDL entity and architecture
code is written to single VHDL file or to separate files |
| SplitEntityFilePostfix | Specify string to append to specified filter name to form
name of file that contains filter's VHDL entity |
| UserComment | Specify comment line in header of generated filter
and test bench files |
| VectorPrefix | Specify string prefixed to vector names in generated VHDL
code |
| VHDLArchitectureName | Specify architecture name for generated VHDL code |
| VHDLLibraryName | Specify target library name used in initialization section
of compilation script |
| AddInputRegister | Generate extra register in HDL code for filter input |
| AddOutputRegister | Generate extra register in HDL code for filter output |
| ClockEnableInputPort | Name HDL port for filter's clock enable input signals |
| ClockEnableOutputPort | For multirate filters (with single clock), specify name
of clock enable output port |
| ClockInputPort | Name HDL port for filter's clock input signals |
| ClockInputs | For multirate filters, specify generation of single or
multiple clock inputs |
| FracDelayPort | Name port for Farrow filter's fractional delay input signal |
| InputComplex | Enable generation ports and signal paths that correspond
to filters with complex input data |
| InputDataType | Specify input data type for system objects for HDL code
generation |
| InputPort | Name HDL port for filter's input signals |
| InputType | Specify HDL data type for filter's input port |
| OutputPort | Name HDL port for filter's output signals |
| OutputType | Specify HDL data type for filter's output port |
| ResetInputPort | Name HDL port for filter's reset input signals |
| AddRatePort | Generate rate ports for variable-rate CIC filter |
| BlockGenerateLabel | Specify string to append to block labels used for HDL GENERATE statements |
| CastBeforeSum | Enable or disable type casting of input values for addition
and subtraction operations |
| CoefficientMemory | Specify type of memory for storage of programmable coefficients
for serial FIR filters |
| CoefficientSource | Specify source for FIR or IIR filter coefficients |
| InlineConfigurations | Specify whether generated VHDL code includes inline configurations |
| InstanceGenerateLabel | Specify string to append to instance section labels in
VHDL GENERATE statements |
| LoopUnrolling | Specify whether VHDL FOR and GENERATE loops
are unrolled and omitted from generated VHDL code |
| OutputGenerateLabel | Specify string that labels output assignment block for
VHDL GENERATE statements |
| SafeZeroConcat | Specify syntax used in generated VHDL code for concatenated
zeros |
| UseAggregatesForConst | Specify whether all constants are represented by aggregates,
including constants that are less than 32 bits wide |
| UseRisingEdge | Specify VHDL coding style used to check for rising edges
when operating on registers |
| UseVerilogTimescale | Allow or exclude use of compiler ˋtimescale directives in generated Verilog
code |
| AddPipelineRegisters | Optimize clock rate used by filter code by adding pipeline
registers |
| CoeffMultipliers | Specify technique used for processing coefficient multiplier
operations |
| DALUTPartition | Specify number and size of LUT partitions for distributed
arithmetic architecture |
| DARadix | Specify number of bits processed simultaneously in distributed
arithmetic architecture |
| FIRAdderStyle | Specify final summation technique used for FIR filters |
| FoldingFactor | Specify folding factor for IIR SOS filter with serial
architecture |
| MultiplierInputPipeline | Specify number of pipeline stages at multiplier inputs
for FIR filters |
| MultiplierOutputPipeline | Specify number of pipeline stages at multiplier outputs
for FIR filters |
| NumMultipliers | Specify multipliers for IIR SOS filter with serial architecture |
| OptimizeForHDL | Specify whether generated HDL code is optimized for specific
performance or space requirements |
| ReuseAccum | Enable accumulator reuse, generating cascade-serial architecture
for FIR filters |
| SerialPartition | Specify number and size of partitions generated for serial
filter architectures |
| ClockHighTime | Specify period, in nanoseconds, during which test bench
drives clock input signals high (1) |
| ClockLowTime | Specify period, in nanoseconds, during which test bench
drives clock input signals low (0) |
| ErrorMargin | Specify error margin for HDL language-based test benches |
| ForceClock | Specify whether test bench forces clock input signals |
| ForceClockEnable | Specify whether test bench forces clock enable input signals |
| ForceReset | Specify whether test bench forces reset input signals |
| GenerateCoSimBlock | Generate model containing HDL Cosimulation block(s) for
simulation of filter in Simulink |
| GenerateCosimModel | Generate model containing realized filter and HDL Cosimulation
block for simulation of filter in Simulink |
| GenerateHDLTestbench | Enable generation of a test bench |
| HoldInputDataBetweenSamples | Specify how long input data values are held in valid state |
| HoldTime | Specify hold time for filter data input signals and forced
reset input signals |
| InitializeTestBenchInputs | Specify initial value driven on test bench inputs before
data is asserted to filter |
| MultifileTestBench | Divide generated test bench into helper functions, data,
and HDL test bench code files |
| SimulatorFlags | Specify simulator flags applied to generated test bench |
| TestBenchClockEnableDelay | Define elapsed time (in clock cycles) between deassertion
of reset and assertion of clock enable |
| TestbenchCoeffStimulus | Specify testing options for coefficient memory interface
for FIR or IIR filters |
| TestBenchDataPostFix | Specify suffix added to test bench data file name when
generating multi-file test bench |
| TestBenchFracDelayStimulus | Specify input stimulus that test bench applies to Farrow
filter fractional delay port |
| TestBenchName | Name VHDL test bench entity or Verilog module and file
that contains test bench code |
| TestbenchRateStimulus | Specify rate stimulus for CIC filter with rate port |
| TestBenchReferencePostFix | Specify string appended to names of reference signals
generated in test bench code |
| TestBenchStimulus | Specify input stimuli that test bench applies to filter
|
| TestBenchUserStimulus | Specify user-defined function that returns vector of values
that test bench applies to filter |
| EDAScriptGeneration | Enable or disable generation of script files for third-party
tools |
| HDLCompileFilePostfix | Specify postfix string appended to file name for generated Mentor Graphics ModelSim compilation
scripts |
| HDLCompileInit | Specify string written to initialization section of compilation
script |
| HDLCompileTerm | Specify string written to termination section of compilation
script |
| HDLCompileVerilogCmd | Specify command string written to compilation script for
Verilog files |
| HDLCompileVHDLCmd | Specify command string written to compilation script for
VHDL files |
| HDLSimCmd | Specify simulation command written to simulation script |
| HDLSimFilePostfix | Specify postfix string appended to file name for generated Mentor Graphics ModelSim simulation
scripts |
| HDLSimInit | Specify string written to initialization section of simulation
script |
| HDLSimTerm | Specify string written to termination section of simulation
script |
| HDLSimViewWaveCmd | Specify waveform viewing command written to simulation
script |
| HDLSynthCmd | Specify command written to synthesis script |
| HDLSynthFilePostfix | Specify postfix string appended to file name for generated Synplify synthesis
scripts |
| HDLSynthInit | Specify string written to initialization section of synthesis
script |
| HDLSynthTerm | Specify string written to termination section of synthesis
script |
| HDLSynthTool | Select synthesis tool for which the coder generates scripts. |
Alphabetical List
