Properties — Alphabetical List

By Category

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AddInputRegister
AddOutputRegister
AddPipelineRegisters
AddRatePort
BlockGenerateLabel
CastBeforeSum
ClockEnableInputPort
ClockEnableOutputPort
ClockHighTime
ClockInputPort
ClockInputs
ClockLowTime
ClockProcessPostfix
CoefficientMemory
CoefficientSource
CoeffMultipliers
CoeffPrefix
ComplexImagPostfix
ComplexRealPostfix
DALUTPartition
DARadix
EDAScriptGeneration
EntityConflictPostfix
ErrorMargin
FIRAdderStyle
FoldingFactor
ForceClock
ForceClockEnable
ForceReset
FracDelayPort
GenerateCoSimBlock
GenerateCosimModel
GenerateHDLTestbench
HDLCompileFilePostfix
HDLCompileInit
HDLCompileTerm
HDLCompileVerilogCmd
HDLCompileVHDLCmd
HDLSimCmd
HDLSimFilePostfix
HDLSimInit
HDLSimTerm
HDLSimViewWaveCmd
HDLSynthCmd
HDLSynthFilePostfix
HDLSynthInit
HDLSynthTerm
HDLSynthTool
HoldInputDataBetweenSamples
HoldTime
InitializeTestBenchInputs
InlineConfigurations
InputComplex
InputDataType
InputPort
InputType
InstanceGenerateLabel
InstancePrefix
LoopUnrolling
MultifileTestBench
MultiplierInputPipeline
MultiplierOutputPipeline
Name
NumMultipliers
OptimizeForHDL
OutputGenerateLabel
OutputPort
OutputType
PackagePostfix
RemoveResetFrom
ReservedWordPostfix
ResetAssertedLevel
ResetInputPort
ResetLength
ResetType
ReuseAccum
SafeZeroConcat
SerialPartition
SimulatorFlags
SplitArchFilePostfix
SplitEntityArch
SplitEntityFilePostfix
TargetDirectory
TargetLanguage
TestBenchClockEnableDelay
TestbenchCoeffStimulus
TestBenchDataPostFix
TestBenchFracDelayStimulus
TestBenchName
TestbenchRateStimulus
TestBenchReferencePostFix
TestBenchStimulus
TestBenchUserStimulus
UseAggregatesForConst
UserComment
UseRisingEdge
UseVerilogTimescale
VectorPrefix
VerilogFileExtension
VHDLArchitectureName
VHDLFileExtension
VHDLLibraryName

Property Reference

Function Reference

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