AddPipelineRegisters - Optimize clock rate used by filter code by adding pipeline registers

Settings

'on'

Add a pipeline register between stages of computation in a filter. For example, for a sixth-order IIR filter, the coder adds two pipeline registers, one between the first and second sections and one between the second and third sections. Although the registers add to the overall filter latency, they provide significant improvements to the clock rate.

For...	A Pipeline Register Is Added Between...
FIR Transposed filters	Coefficient multipliers and adders
FIR, Asymmetric FIR, and Symmetric FIR filters	Levels of a tree-based final adder
IIR filters	Sections

'off' (default)

Suppress the use of pipeline registers.

Usage Notes

For FIR filters, the use of pipeline registers optimizes filter final summation. For details, see Optimizing Final Summation for FIR Filters.

Note   The use of pipeline registers in FIR, antisymmetric FIR, and symmetric FIR filters can produce numeric results that differ from those produced by the original filter object because they force the tree mode of final summation. In such cases, consider adjusting the test bench error margin.

See Also

CoeffMultipliers, FIRAdderStyle, OptimizeForHDL

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