Digital Down Converter (DDC) and Digital Up Converter (DUC) System Objects :: HDL Code for Supported Filter Structures (Filter Design HDL Coder™)

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R2012a Documentation → Filter Design HDL Coder
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Contents

Index

• Getting Started

• User's Guide

• HDL Filter Code Generation Essentials

• HDL Code for Supported Filter Structures

• Multirate Filters

• Variable Rate CIC Filters

• Cascade Filters

• Polyphase Sample Rate Converters

• Multirate Farrow Sample Rate Converters

• Single-Rate Farrow Filters

• Programmable Filter Coefficients for FIR Filters

• Programmable Filter Coefficients for IIR Filters

• Digital Down Converter (DDC) and Digital Up Converter (DUC) System Objects

• Optimization of HDL Filter Code

Overview of Speed vs. Area Optimizations

Parallel and Serial Architectures

Specifying Speed vs. Area Tradeoffs via generatehdl Properties

Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box

Distributed Arithmetic Overview

Requirements and Considerations for Generating Distributed Arithmetic Code

DALUTPartition Property

DARadix Property

Specifying Distributed Arithmetic for Cascaded Filters

Distributed Arithmetic Options in the Generate HDL Dialog Box

Optimizing the Clock Rate with Pipeline Registers

Multiplier Input and Output Pipelining for FIR Filters

Optimizing Final Summation for FIR Filters

Specifying or Suppressing Registered Input and Output

Overall HDL Filter Optimization

Setting an Error Margin for Optimized Filter Code

• Customization of HDL Filter Code

Setting the Location of Generated Files

Naming the Generated Files and Filter Entity

Setting File Name Extensions

Splitting Entity and Architecture Code Into Separate Files

Specifying a Header Comment

Resolving Entity or Module Name Conflicts

Resolving HDL Reserved Word Conflicts

Setting the Postfix String for VHDL Package Files

Specifying a Prefix for Filter Coefficients

Specifying a Postfix String for Process Block Labels

Setting a Prefix for Component Instance Names

Setting a Prefix for Vector Names

Naming HDL Ports

Specifying the HDL Data Type for Data Ports

Selecting Asynchronous or Synchronous Reset Logic

Setting the Asserted Level for the Reset Input Signal

Suppressing Generation of Reset Logic

Representing VHDL Constants with Aggregates

Unrolling and Removing VHDL Loops

Using the VHDL rising_edge Function

Suppressing the Generation of VHDL Inline Configurations

Specifying VHDL Syntax for Concatenated Zeros

Specifying Input Type Treatment for Addition and Subtraction Operations

Suppressing Verilog Time Scale Directives

Using Complex Data and Coefficients

• Verification of Generated HDL Filter Code

Workflow for Testing With an HDL Test Bench

Enabling Test Bench Generation

Renaming the Test Bench

Specifying a Test Bench Type

Splitting Test Bench Code and Data into Separate Files

Configuring the Clock

Configuring Resets

Setting a Hold Time for Data Input Signals

Setting an Error Margin for Optimized Filter Code

Setting an Initial Value for Test Bench Inputs

Setting Test Bench Stimuli

Setting a Postfix for Reference Signal Names

Generating HDL Cosimulation Blocks for Use with HDL Simulators

Generating a Simulink Model for Cosimulation with an HDL Simulator

Generating a Default Script

Customizing Script Generation Using CLI Properties

Customizing Script Generation with the EDA Tool Scripts Dialog Box

• Synthesis and Workflow Automation

Selecting a Synthesis Tool

Customizing Synthesis Script Generation Using CLI Properties

Customizing Synthesis Script Generation with the EDA Tool Scripts Dialog Box

• Property Reference

• Release Notes

Digital Down Converter (DDC) and Digital Up Converter (DUC) System Objects

You can generate HDL code for DUC and DDC System objects, giving you a direct path from System object to hardware. This capability is limited to code generation at the command line only.

The command line interface now includes the property InputDataType. This property accepts only numerictype values.

>> hDDC = dsp.DigitalDownConverter('Oscillator','NCO');
>> generatehdl(hDDC, 'InputDataType', numerictype([], 8,7));

The software generates a data valid signal at the top DDC or DUC level:

For DDC, the signal is named ce_out. Filter Design HDL Coder™ software ties that signal to the corresponding ce_out signal from the decimating filtering cascade.
For DUC, the signal is named ce_out_valid. The coder software ties that signal to the corresponding ce_out_valid signal from the interpolating filtering cascade.

Limitations

You may not set the input and output port names. These ports have the default names of ddc_in and ddc_out. Inputs and outputs are always registered by the software. If you attempt to turn them off, you will get a warning.

You can implement filtering stages in DDC and DUC with the default fully parallel architecture only. For these objects, the coder software does not support optimization and architecture-specific properties such as:

SerialPArtition
DALUTPArtition
DARAdix
AddpipelineRegisters
MultiplierInputPipleine
MultiplierOutputPipelines

Programmable Filter
Coefficients for IIR Filters

Programmable Filter Coefficients for IIR Filters

Optimization of HDL Filter Code

Optimization of HDL Filter Code

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