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| R2012a Documentation → Filter Design HDL Coder | |
Learn more about Filter Design HDL Coder |
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Set up a writable working folder outside your MATLAB installation folder to store files that will be generated as you complete your tutorial work. The tutorial instructions assume that you create the folder hdlfilter_tutorials on drive C.
This tutorial guides you through the steps for designing a basic quantized discrete-time FIR filter, generating VHDL code for the filter, and verifying the VHDL code with a generated test bench.
This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool). The following instructions guide you through the procedure of designing and creating a basic FIR filter using FDATool:
Start the MATLAB software.
Set your current folder to the folder you created in Creating a Folder for Your Tutorial Files.
Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.
In the Filter Design & Analysis Tool dialog box, check that the following filter options are set:
| Option | Value |
|---|---|
| Response Type | Lowpass |
| Design Method | FIR Equiripple |
| Filter Order | Minimum order |
| Options | Density Factor: 20 |
| Frequency Specifications | Units: Hz Fs: 48000 Fpass: 9600 Fstop: 12000 |
| Magnitude Specifications | Units: dB Apass: 1 Astop: 80 |
These settings are for the default filter design that the FDATool creates for you. If you do not need to make any changes and Design Filter is grayed out, you are done and can skip to Quantizing the FIR Filter.
If you modified any of the options listed in step 4, click Design Filter. The FDATool creates a filter for the specified design and displays the following message in the FDATool status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the FDATool, see the DSP System Toolbox documentation.
You should quantize filters for HDL code generation. To quantize your filter,
Open the basic FIR filter design you created in Designing a Basic FIR Filter in FDATool.
Click the Set Quantization Parameters
button
in the left-side toolbar.
The FDATool displays a Filter arithmetic menu
in the bottom half of its dialog box.
Select Fixed-point from the Filter arithmetic list. Then select Specify all from the Filter precision list. The FDATool displays the first of three tabbed panels of quantization parameters across the bottom half of its dialog box.
You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.
Set the quantization parameters as follows:
| Tab | Parameter | Setting |
|---|---|---|
| Coefficients | Numerator word length | 16 |
| Best-precision fraction lengths | Selected | |
| Use unsigned representation | Cleared | |
| Scale the numerator coefficients to fully utilize the entire dynamic range | Cleared | |
| Input/Output | Input word length | 16 |
| Input fraction length | 15 | |
| Output word length | 16 | |
| Filter Internals | Rounding mode | Floor |
| Overflow mode | Saturate | |
| Accum. word length | 40 |
Click Apply.
For more information on quantizing filters with the FDATool, see the DSP System Toolbox documentation.
After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the basic FIR filter you designed and quantized in Designing a Basic FIR Filter in FDATool and Quantizing the Basic FIR Filter
Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.
Find the Filter Design HDL Coder online help. Use the online help to learn about product details or to get answers to questions as you work with the designer.
In the MATLAB window, click the Help button in the toolbar or click Help > Product Help.
In the Help browser's Contents pane, select the Filter Design HDL Coder entry.
Minimize the Help browser.
In the Generate HDL dialog box, click the Help button. A small context-sensitive help window opens. The window displays information about the dialog box.
Close the Help window.
Place your cursor over the Folder label or text box in the Target pane of the Generate HDL dialog box, and right-click. A What's This? button appears.
Click What's This? The context-sensitive help window displays information describing the Folder option. Use the context-sensitive help while using the GUI to configure the contents and style of the generated HDL code. A help topic is available for each option.
In the Name text box of the Target pane, replace the default name with basicfir. This option names the VHDL entity and the file that is to contain the filter's VHDL code.
Select the Global settings tab of the GUI. Then select the General tab of the Additional settings section of the GUI. Type Tutorial - Basic FIR Filter in the Comment in header text box. The coder adds the comment to the end of the header comment block in each generated file.
Select the Ports tab of the Additional settings section of the GUI.
Change the names of the input and output ports. In the Input port text box, replace filter_in with data_in. In the Output port text box, replace filter_out with data_out.
Clear the check box for the Add input register option. The Ports pane should now look like the following.
Click on the Test Bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with basicfir_tb. This option names the generated test bench file.
Click Generate to start the code generation process.
The coder displays messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:
### Starting VHDL code generation process for filter: basicfir ### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd ### Starting generation of basicfir VHDL entity ### Starting generation of basicfir VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: basicfir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3429 samples. ### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd ### Please wait ... ### Done generating VHDL Test Bench >>
As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the files basicfir.vhd and basicfir_tb.vhd in that folder.
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated VHDL code has the following characteristics:
VHDL entity named basicfir.
Registers that use asynchronous resets when the reset signal is active high (1).
Ports have the following names:
| VHDL Port | Name |
|---|---|
| Input | data_in |
| Output | data_out |
| Clock input | clk |
| Clock enable input | clk_enable |
| Reset input | reset |
An extra register for handling filter output.
Clock input, clock enable input and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR.
Coefficients are named coeffn, where n is the coefficient number, starting with 1.
Type safe representation is used when zeros are concatenated: '0' & '0'...
Registers are generated with the statement ELSIF clk'event AND clk='1' THEN rather than with the rising_edge function.
The postfix string _process is appended to process names.
The generated test bench:
Is a portable VHDL file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
For a FIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
When you have finished generating code, click Close to close the Generate HDL dialog box.
Get familiar with the filter's generated VHDL code by opening and browsing through the file basicfir.vhd in an ASCII or HDL simulator editor:
Open the generated VHDL filter file basicfir.vhd.
Search for basicfir. This line identifies the VHDL module, using the string you specified for the Name option in the Target pane. See step 5 in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 10 in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for HDL Code. This section lists coder options you modified in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for Filter Settings. This section describes the filter design and quantization settings as you specified in Designing a Basic FIR Filter in FDATool and Quantizing the Basic FIR Filter.
Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the Target pane. See step 5 in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, and reset signals are named with default strings. The ports for data input and output are named with the strings you specified for the Input port and Output port options on the Ports tab of the Generate HDL dialog box. See step 12 in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for Constants. This is where the coefficients are defined. They are named using the default naming scheme,coeffn, where n is the coefficient number, starting with 1.
Search for Signals. This is where the filter's signals are defined.
Search for process. The PROCESS block name Delay_Pipeline_process includes the default PROCESS block postfix string _process.
Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset style when generating VHDL code for registers.
Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on registers. The default ELSIF clk'event statement is used instead of the optional rising_edge function.
Search for Output_Register. This is where filter output is written to an output register. Code for this register is generated by default. In step 13 in Configuring and Generating the Basic FIR Filter's VHDL Code, you cleared the Add input register option, but left the Add output register selected. Also note that the PROCESS block name Output_Register_process includes the default PROCESS block postfix string _process.
Search for data_out. This is where the filter writes its output data.
This section explains how to verify the basic FIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses the Mentor Graphics® ModelSim® software as the tool for compiling and simulating the VHDL code, you can use any VHDL simulation tool package.
To verify the filter code, complete the following steps:
Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears.
Set the current folder to the folder that contains your generated VHDL files. For example:
cd c:/hdlfilter_tutorials/hdlsrc
If desired, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In the Mentor Graphics ModelSim simulator, you can create a design library with the vlib command.
vlib work
Compile the generated filter and test bench VHDL files. In the Mentor Graphics ModelSim simulator, you compile VHDL code with the vcom command. The following commands compile the filter and filter test bench VHDL code.
vcom basicfir.vhd vcom basicfir_tb.vhd
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:
vsim work.basicfir_tb
The following figure shows the results of loading work.basicfir_tb with the vsim command.
Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms:
add wave *
The following wave window displays.
To start running the simulation, issue the start simulation command for your simulator. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run command.
The following display shows the run -all command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
Note The failure message that appears in the preceding display is not flagging an actual error. If the message includes the string Test Complete, the test bench has run to completion without encountering any errors. The Failure part of the message is tied to the mechanism that the coder uses to end the simulation. |
The following wave window shows the simulation results as HDL waveforms.
Configuring and Generating the FIR Filter's Optimized Verilog Code
Getting Familiar with the FIR Filter's Optimized Generated Verilog Code
This tutorial guides you through the steps for designing an optimized quantized discrete-time FIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.
This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool).
Start the MATLAB software.
Set your current folder to the folder you created in Creating a Folder for Your Tutorial Files.
Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.
In the Filter Design & Analysis Tool dialog box, set the following filter options:
| Option | Value |
|---|---|
| Response Type | Lowpass |
| Design Method | FIR Equiripple |
| Filter Order | Minimum order |
| Options | Density Factor: 20 |
| Frequency Specifications | Units: Hz Fs: 48000 Fpass: 9600 Fstop: 12000 |
| Magnitude Specifications | Units: dB Apass: 1 Astop: 80 |
These settings are for the default filter design that the FDATool creates for you. If you do not need to make any changes and Design Filter is grayed out, you are done and can skip to Quantizing the Basic FIR Filter.
Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the FDATool, see the DSP System Toolbox documentation.
You should quantize filters for HDL code generation. To quantize your filter,
Open the FIR filter design you created in Optimized FIR Filter if it is not already open.
Click the Set Quantization Parameters button
in
the left-side toolbar. The FDATool displays a Filter arithmetic menu
in the bottom half of its dialog box.
Select Fixed-point from the list. Then select Specify all from the Filter precision list. The FDATool displays the first of three tabbed panels of quantization parameters across the bottom half of its dialog box.
You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.
Set the quantization parameters as follows:
| Tab | Parameter | Setting |
|---|---|---|
| Coefficients | Numerator word length | 16 |
| Best-precision fraction lengths | Selected | |
| Use unsigned representation | Cleared | |
| Scale the numerator coefficients to fully utilize the entire dynamic range | Cleared | |
| Input/Output | Input word length | 16 |
| Input fraction length | 15 | |
| Output word length | 16 | |
| Filter Internals | Rounding mode | Floor |
| Overflow mode | Saturate | |
| Accum. word length | 40 |
Click Apply.
For more information on quantizing filters with the FDATool, see the DSP System Toolbox documentation.
After you quantize your filter, you are ready to configure coder options and generate the filter's Verilog code. This section guides you through the process for starting the GUI, setting some options, and generating the Verilog code and a test bench for the FIR filter you designed and quantized in Designing the FIR Filter in FDATool and Quantizing the FIR Filter.
Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.
Select Verilog for the Language option, as shown in the following figure.
In the Name text box of the Target pane, replace the default name with optfir. This option names the Verilog module and the file that is to contain the filter's Verilog code.
In the Filter architecture pane, select the Optimize for HDL option. This option is for generating HDL code that is optimized for performance or space requirements. When this option is enabled, the coder makes tradeoffs concerning data types and might ignore your quantization settings to achieve optimizations. When you use the option, keep in mind that you do so at the cost of potential numeric differences between filter results produced by the original filter object and the simulated results for the optimized HDL code.
Select CSD for the Coefficient multipliers option. This option optimizes coefficient multiplier operations by instructing the coder to replace them with additions of partial products produced by a canonic signed digit (CSD) technique. This technique minimizes the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits.
Select the Add pipeline registers option. For FIR filters, this option optimizes final summation. The coder creates a final adder that performs pair-wise addition on successive products and includes a stage of pipeline registers after each level of the tree. When used for FIR filters, this option also has the potential for producing numeric differences between results produced by the original filter object and the simulated results for the optimized HDL code.
The Generate HDL dialog box should now appear as shown in the following figure.
Select the Global settings tab of the GUI. Then select the General tab of the Additional settings section.
In the Comment in header text box, type Tutorial - Optimized FIR Filter. The coder adds the comment to the end of the header comment block in each generated file.
Select the Ports tab of the Additional settings section of the GUI.
Change the names of the input and output ports. In the Input port text box, replace filter_in with data_in. In the Output port text box, replace filter_out with data_out.
Clear the check box for the Add input register option. The Ports pane should now look like the following.
Click on the Test Bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with optfir_tb. This option names the generated test bench file.
In the Test Bench pane, click the Configuration tab. Observe that the Error margin (bits) option is enabled. This option is enabled because previously selected optimization options (such as Add pipeline registers) can potentially produce numeric results that differ from the results produced by the original filter object. You can use this option to adjust the number of least significant bits the test bench will ignore during comparisons before generating a warning.
In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click Close to close the dialog box.
The coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench Verilog files:
### Starting Verilog code generation process for filter: optfir ### Generating: C:\hdlfilter_tutorials\hdlsrc\optfir.v ### Starting generation of optfir Verilog module ### Starting generation of optfir Verilog module body ### HDL latency is 8 samples ### Successful completion of Verilog code generation process for filter: optfir ### Starting generation of VERILOG Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3429 samples. ### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\optfir_tb.v ### Please wait ... ### Done generating VERILOG Test Bench
As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the files optfir.v and optfir_tb.v in that folder.
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated Verilog code has the following characteristics:
Verilog module named optfir.
Registers that use asynchronous resets when the reset signal is active high (1).
Generated code that optimizes its use of data types and eliminates redundant operations.
Coefficient multipliers optimized with the CSD technique.
Final summations optimized using a pipelined technique.
Ports that have the following names:
| Verilog Port | Name |
|---|---|
| Input | data_in |
| Output | data_out |
| Clock input | clk |
| Clock enable input | clk_enable |
| Reset input | reset |
An extra register for handling filter output.
Coefficients named coeffn, where n is the coefficient number, starting with 1.
Type safe representation is used when zeros are concatenated: '0' & '0'...
The postfix string _process is appended to sequential (begin) block names.
The generated test bench:
Is a portable Verilog file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
Applies an error margin of 4 bits.
For a FIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
Get familiar with the filter's optimized generated Verilog code by opening and browsing through the file optfir.v in an ASCII or HDL simulator editor:
Open the generated Verilog filter file optcfir.v.
Search for optfir. This line identifies the Verilog module, using the string you specified for the Name option in the Target pane. See step 3 in Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 9 in Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for HDL Code. This section lists the coder options you modified in Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in Designing the FIR Filter in FDATool and Quantizing the FIR Filter.
Search for module. This line names the Verilog module, using the string you specified for the Name option in the Target pane. This line also declares the list of ports, as defined by options on the Ports pane of the Generate HDL dialog box. The ports for data input and output are named with the strings you specified for the Input port and Output port options on the Ports tab of the Generate HDL dialog box. See steps 3 and 11 in Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for input. This line and the four lines that follow, declare the direction mode of each port.
Search for Constants. This is where the coefficients are defined. They are named using the default naming scheme, coeffn, where n is the coefficient number, starting with 1.
Search for Signals. This is where the filter's signals are defined.
Search for sumvector1. This area of code declares the signals for implementing an instance of a pipelined final adder. Signal declarations for four additional pipelined final adders are also included. These signals are used to implement the pipelined FIR adder style optimization specified with the Add pipeline registers option. See step 7 in Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for process. The block name Delay_Pipeline_process includes the default block postfix string _process.
Search for reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the process applies the default asynchronous reset style when generating code for registers.
Search for posedge. This Verilog code checks for rising edges when the filter operates on registers.
Search for sumdelay_pipeline_process1. This block implements the pipeline register stage of the pipeline FIR adder style you specified in step 7 of Configuring and Generating the FIR Filter's Optimized Verilog Code.
Search for output_register. This is where filter output is written to an output register. The code for this register is generated by default. In step 12 in Configuring and Generating the FIR Filter's Optimized Verilog Code , you cleared the Add input register option, but left the Add output register selected. Also note that the process name Output_Register_process includes the default process postfix string _process.
Search for data_out. This is where the filter writes its output data.
This section explains how to verify the FIR filter's optimized generated Verilog code with the generated Verilog test bench. Although this tutorial uses the Mentor Graphics ModelSim simulator as the tool for compiling and simulating the Verilog code, you can use any HDL simulation tool package.
To verify the filter code, complete the following steps:
Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears.
Set the current folder to the folder that contains your generated Verilog files. For example:
cd hdlsrc
If desired, create a design library to store the compiled Verilog modules. In the Mentor Graphics ModelSim simulator, you can create a design library with the vlib command.
vlib work
Compile the generated filter and test bench Verilog files. In the Mentor Graphics ModelSim simulator, you compile Verilog code with the vlog command. The following commands compile the filter and filter test bench Verilog code.
vlog optfir.v vlog optfir_tb.v
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:
vsim optfir_tb
The following display shows the results of loading optfir_tb with the vsim command.
Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms:
add wave *
The following wave window opens:
To start running the simulation, issue the start simulation command for your simulator. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run command.
The following display shows the run -all command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter Verilog code.
The following wave window shows the simulation results as HDL waveforms.
This tutorial guides you through the steps for designing an IIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.
This section guides you through the procedure of designing and creating a filter for an IIR filter. This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool).
Start the MATLAB software.
Set your current folder to the folder you created in Creating a Folder for Your Tutorial Files.
Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.
In the Filter Design & Analysis Tool dialog box, set the following filter options:
| Option | Value |
|---|---|
| Response Type | Highpass |
| Design Method | IIR Butterworth |
| Filter Order | Specify order:5 |
| Frequency Specifications | Units: Hz Fs: 48000 Fc: 10800 |
Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the FDATool, see Use FDATool with DSP System Toolbox Software in the DSP System Toolbox documentation.
You should quantize filters for HDL code generation. To quantize your filter,
Open the IIR filter design you created in Designing an IIR Filter in FDATool if it is not already open.
Click the Set Quantization Parameters button
in
the left-side toolbar. The FDATool displays the Filter arithmetic list
in the bottom half of its dialog box.
Select Fixed-point from the list. The FDATool displays the first of three tabbed panels of its dialog box.
You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.
Select the Filter Internals tab and set Rounding mode to Floor and Overflow Mode to Saturate.
Click Apply. The quantized filter appears as follows.
For more information on quantizing filters with the FDATool, see Use FDATool with DSP System Toolbox Software in the DSP System Toolbox documentation.
After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the IIR filter you designed and quantized in Designing an IIR Filter in FDATool and Quantizing the IIR Filter:
Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.
In the Name text box of the Target pane, type iir. This option names the VHDL entity and the file that will contain the filter's VHDL code.
Select the Global settings tab of the GUI. Then select the General tab of the Additional settings section.
In the Comment in header text box, type Tutorial - IIR Filter. The coder adds the comment to the end of the header comment block in each generated file.
Select the Ports tab. The Ports pane appears.
Clear the check box for the Add output register option. The Ports pane should now appear as in the following figure.
Select the Advanced tab. The Advanced pane appears.
Select the Use 'rising_edge' for registers option. The Advanced pane should now appear as in the following figure.
Click on the Test bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with iir_tb. This option names the generated test bench file.
In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click OK to close the dialog box.
The coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:
### Starting VHDL code generation process for filter: iir ### Starting VHDL code generation process for filter: iir ### Generating: H:\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2 ### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 2172 samples. ### Generating Test bench: H:\hdlsrc\filter_tb.vhd ### Please wait ... ### Done generating VHDL Test Bench ### Starting VHDL code generation process for filter: iir ### Starting VHDL code generation process for filter: iir ### Generating: H:\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### Second-order section, # 1 ### Second-order section, # 2 ### First-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir
As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the files iir.vhd and iir_tb.vhd in that folder.
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated VHDL code has the following characteristics:
VHDL entity named iir.
Registers that use asynchronous resets when the reset signal is active high (1).
Ports have the following default names:
| VHDL Port | Name |
|---|---|
| Input | filter_in |
| Output | filter_out |
| Clock input | clk |
| Clock enable input | clk_enable |
| Reset input | reset |
An extra register for handling filter input.
Clock input, clock enable input and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR.
Coefficients are named coeffn, where n is the coefficient number, starting with 1.
Type safe representation is used when zeros are concatenated: '0' & '0'...
Registers are generated with the rising_edge function rather than the statement ELSIF clk'event AND clk='1' THEN.
The postfix string _process is appended to process names.
The generated test bench:
Is a portable VHDL file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
For an IIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
Get familiar with the filter's generated VHDL code by opening and browsing through the file iir.vhd in an ASCII or HDL simulator editor:
Open the generated VHDL filter file iir.vhd.
Search for iir. This line identifies the VHDL module, using the string you specified for the Name option in the Target pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.
Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 5 in Configuring and Generating the IIR Filter's VHDL Code.
Search for HDL Code. This section lists coder options you modified inConfiguring and Generating the IIR Filter's VHDL Code.
Search for Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in Designing an IIR Filter in FDATool and Quantizing the IIR Filter.
Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the Target pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.
Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, reset, and data input and output signals are named with default strings.
Search for CONSTANT. This is where the coefficients are defined. They are named using the default naming scheme, coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number.
Search for SIGNAL. This is where the filter's signals are defined.
Search for input_reg_process. The PROCESS block name input_reg_process includes the default PROCESS block postfix string _process. This is where filter input is read from an input register. Code for this register is generated by default. In step 7 in Configuring and Generating the Basic FIR Filter's VHDL Code, you cleared the Add output register option, but left the Add input register option selected.
Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset style when generating VHDL code for registers.
Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on registers. The rising_edge function is used as you specified in the Advanced pane of the Generate HDL dialog box. See step 10 in Configuring and Generating the Basic FIR Filter's VHDL Code.
Search for Section 1. This is where second-order section 1 data is filtered. Similar sections of VHDL code apply to another second-order section and a first-order section.
Search for filter_out. This is where the filter writes its output data.
This sections explains how to verify the IIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses theMentor Graphics ModelSim simulator as the tool for compiling and simulating the VHDL code, you can use any HDL simulation tool package.
To verify the filter code, complete the following steps:
Start your simulator. When you start theMentor Graphics ModelSim simulator, a screen display similar to the following appears.
Set the current folder to the folder that contains your generated VHDL files. For example:
cd hdlsrc
If desired, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In theMentor Graphics ModelSim simulator, you can create a design library with the vlib command.
vlib work
Compile the generated filter and test bench VHDL files. In the Mentor Graphics ModelSim simulator, you compile VHDL code with the vcom command. The following the commands compile the filter and filter test bench VHDL code.
vcom iir.vhd vcom iir_tb.vhd
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:
vsim work.iir_tb
The following display shows the results of loading work.iir_tb with the vsim command.
Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms.
add wave *
The following wave window displays.
To start running the simulation, issue the start simulation command for your simulator. For example, in theMentor Graphics ModelSim simulator, you can start a simulation with the run command.
The following display shows the run -all command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
Note
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The following wave window shows the simulation results as HDL waveforms.
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