Architecture Options for Cascaded Filters

You can specify serial, DA, or parallel architectures for individual stages of cascade filters. These options lead to an area efficient implementation of cascade filters, such as Digital Down Converter (DDC), Digital Up Converter (DUC), and so on. You can use this feature only with the command-line interface (generatehdl).

You can pass a cell array of values to the ‘SerialPartition', ‘DALUTPartition', and ‘DARadix' properties, with each element corresponding to its respective stage. You can also pass the default values if you want to skip the corresponding specification for a stage:

• –1 for SerialPartition

• –1 for DALUTPartition

• 2 for DARadix

When you create a cascaded filter, Filter Design HDL Coder software performs the following actions:

• Generates code for each stage as per the inferred architecture.

• Generates an overall timing controller at the top level. This controller then produces clock enables for the module in each stage, which corresponds to that module's rate and folding factor.

Tip   Use the hdlfilterserialinfo function to display the effective filter length and partitioning options for each filter stage of a cascade.

Cascaded Filter with Serial Partitioning

To specify serial partitioning for one or more cascade stages, use the SerialPartition property. The following example defines different serial partitions for each filter in a two-stage cascade. The code implements each stage using two multipliers per stage. The partition vectors reside within a cell array.

Hd = design(fdesign.lowpass('N,Fc',8,.4));
Hd.arithmetic = 'fixed';
Hp = design(fdesign.highpass('N,Fc',8,.4));
Hp.arithmetic = 'fixed';
Hc=cascade(Hd,Hp);
sp1 = hdlfilterserialinfo(Hc.stage(1),'Multiplier', 2);
sp2 = hdlfilterserialinfo(Hc.stage(2),'Multiplier', 2);
generatehdl(Hc,'serialpartition', {sp2, sp2});

Cascaded Filter with DA Architecture

To specify a DA architecture for one or more cascade stages, use the DALUTPartition property. Optionally, you can specify the DARadix property. The following example defines LUT partitions for each filter in a two-stage cascade. The first stage uses LUTs with a max address size of 5 bits and the second stage uses LUTs with a max address size of 3 bits. The DALUT partition vectors and DARadix values reside within a cell array for each property value.

Hd = design(fdesign.lowpass('N,Fc',8,.4));
Hd.arithmetic = 'fixed';
Hp = design(fdesign.highpass('N,Fc',8,.4));
Hp.arithmetic = 'fixed';
Hc=cascade(Hd,Hp);
dp1 = hdlfilterdainfo(Hc.stage(1),'LUTInputs',5);
dp2 = hdlfilterdainfo(Hc.stage(2),'LUTInputs',3);
generatehdl(Hc,'DALUTPartition', {dp1,dp2});

Tip   Use the hdlfilterdainfo function to display the effective filter length, LUT partitioning options, and DARadix values for each filter stage of a cascade.

Cascaded Filter with Multiple Architectures

You can specify a mix of serial, DA, and parallel architectures depending upon your hardware constraints. This example implements DA, serial, and parallel architectures for the first, second, and third stages, respectively.

% create a filter object
h1 = dfilt.dffir([0.05 -.25 .88 0.9 .88 -.25 0.05]);
h1.Arithmetic = 'fixed';
h2 = dfilt.dfasymfir([-0.008 0.06 -0.44 0.44 -0.06 0.008]);
h2.Arithmetic = 'fixed';
h3 = dfilt.dfsymfir([-0.008 0.06 0.44 0.44 0.06 -0.008]);
h3.Arithmetic = 'fixed';
% generate HDL with mixed architectures
Generatehdl(Hd, 'serialpartition',{-1,3,-1},'DaLUTPartition',{[4 3],-1,-1},...
    'DaRadix',{2^8,2,2})

Distributed Arithmetic for FIR Filters

CSD Optimizations for Coefficient Multipliers

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