ErrorMargin - Specify error margin for HDL language-based test benches

Settings

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Some HDL optimizations can generate test bench code that produces numeric results that differ from those produced by the original filter function. By specifying an error margin, you can specify an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning.

Specify the error margin as an integer number of bits.

Usage Notes

Optimizations that can generate test bench code that produces numeric results that differ from those produced by the original filter function include

• CastBeforeSum (qfilts only)

• OptimizeForHDL

• FIRAdderStyle ('Tree')

• AddPipelineRegisters (for FIR, Asymmetric FIR, and Symmetric FIR filters)

The error margin is the number of least significant bits a Verilog or VHDL language-based test bench can ignore when comparing the numeric results before generating a warning.

For fixed-point filters, the Error margin (bits) value is initialized to a default value of 4.

See Also

AddPipelineRegisters, CastBeforeSum, CoeffMultipliers, FIRAdderStyle, OptimizeForHDL

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