generatehdl - Generate HDL code for quantized filter

Syntax

generatehdl(Hd)
generatehdl(Hd 'PropertyName', 'PropertyValue',...)

Description

generatehdl(Hd) generates HDL code for a quantized filter. The argument Hd must be a handle to a filter object. The function uses default settings for properties that determine file and HDL element naming, whether optimizations are applied, HDL coding styles, and test bench characteristics. The defaults are summarized below.

Defaults for Naming, Location and Packaging of Generated Files

• Places generated files in the target folder hdlsrc and names the files as follows:

  File	Name
  Verilog source	Hd.v, where Hd is the name of the specified filter object
  VHDL source	Hd.vhd, where Hd is the name of the specified filter object
  VHDL package	Hd_pkg.vhd, where Hd is the name of the specified filter object

• Places generated files in a subfolder name hdlsrc, under your current working folder.

• Includes the VHDL entity and architecture code in a single source file.

• Generates script files for third-party EDA tools. Where Hd is the name of the specified filter object, the following script files are generated:

  • Hd_compile.do :Mentor Graphics ModelSim compilation script. This script contains commands to compile the generated filter code, but not to simulate it.

  • Hd_synplify.tcl : Synplify synthesis script

Default Settings for Register Resets

• Uses an asynchronous reset when generating HDL code for registers.

• Uses an active-high (1) signal for register resets.

Default Settings for General HDL Code

• Names the generated VHDL entity or Verilog module with the name of the quantized filter.

• Names a filter's HDL ports as follows:

  HDL Port	Name
  Input	filter_in
  Output	filter_out
  Clock input	clk
  Clock enable input	clk_enable
  Reset input	reset

• Sets the data type for clock input, clock enable input, and reset ports to STD_LOGIC and data input and output ports to VHDL type STD_LOGIC_VECTOR or Verilog type wire.

• Names coefficients as follows:

  For...	Names Coefficients...
  FIR filters	coeffn, where n is the coefficient number, starting with 1
  IIR filters	coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number

• When declaring signals of type REAL, initializes the signal with a value of 0.0.

• Places VHDL configurations in any file that instantiates a component.

• Appends _rsvd to names that are VHDL or Verilog reserved words.

• Uses a type safe representation when concatenating zeros: '0' & '0'...

• Applies the statement IF clock'event AND clock='1' THEN to check for clock events.

• Adds an extra input register and an extra output register to the filter.

• Appends _process to process names.

• When creating labels for VHDL GENERATE statements:

  • Appends _gen to section and block names.

  • Names output assignment blocks with the string outputgen.

Default Settings for Code Optimizations

• Generates HDL code that is bit-true to the original filter function and is not optimized for performance or space requirements.

• Applies a linear final summation to FIR filters. This is the form of summation explained in most DSP text books.

• Enables multiplier operations for a filter, as opposed to replacing them with additions of partial products.

generatehdl(Hd 'PropertyName', 'PropertyValue',...) generates HDL code for the filter identified by Hd, using the specified property name and property value pair settings. You can specify the function with one or more of the property name and property value pairs described in Property Reference, and Properties — Alphabetical List.

Examples

1. Design a filter. The call to fdesign in the following command line sequence designs a minimum order lowpass filter with a normalized passband frequency of 0.2, a stopband frequency of 0.22, a passband ripple of 1 dB, and a stopband attenuation of 60 dB.

2. Construct a filter object. The call to design constructs the FIR equiripple filter object Hd.

3. Set the filter arithmetic. The arithmetic assignment statement sets the filter arithmetic to fixed-point arithmetic.

4. Generate VHDL code for the filter. The call to generatehdl generates VHDL code for the FIR equiripple filter Hd. The function names the file MyFilter.vhd and places it in the default target folder hdlsrc.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2, 0.22, 1, 60);
Hd = design(d, 'equiripple');  % Create filter
Hd.arithmetic='fixed';
generatehdl(Hd, 'Name', 'MyFilter'); %Generate VHDL code

How To

• generatetb
• generatetbstimulus

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