generatetb - Generate HDL test bench for filter

Syntax

Description

Note   In Release R2011a, the generatetb function is deprecated. To generate a test bench for your HDL filter code, you should use the generatehdl function, setting the GenerateHDLTestbench property to 'on', as in the following example. generatehdl(Hlp, 'GenerateHDLTestbench', 'on'); In Release R2011a, the generatetb function will continue to operate, but will display a warning message when it is called. You should replace all calls to generatetb in your scripts with calls to generatehdl. This change enables test bench generation with the GenerateHDLTestbench property, as shown in the preceding example.

generatetb(Hd, 'TbType') generates a HDL test bench of a specified type to verify the HDL code generated for the quantized filter identified by Hd. The argument Hd must be a handle to a filter object. The value that you specify for 'TbType' identifies the type of test bench to be generated. This value can be one of those shown in the following table or a cell array that contains one or more of these values.

If you do not specify the 'TbType' argument, the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or 'Verilog').

Specify...	To Generate a Test Bench Consisting of...
'Verilog'	Verilog code
'VHDL'	VHDL code

The generated test bench applies input stimuli based on the setting of the properties TestBenchStimulus and TestBenchUserStimulus. The coder assigns default stimuli based on the filter type. The following choices of stimuli are available:

• 'impulse'

• 'step'

• 'ramp'

• 'chirp'

• 'noise'

The function uses default settings for other properties that determine test bench characteristics.

Default Settings for the Test Bench

• Places the generated test bench file in the target folder hdlsrc under your current working folder. This file has the name Hd_tb and a file type extension that is based on the type of test bench you are generating.

  If the Test Bench Is a...	The Extension Is...
  Verilog file	Defined by the property VerilogFileExtension
  VHDL file	Defined by the property VHDLFileExtension

• Generates script files for third-party EDA tools. Where Hd is the name of the specified filter object, the following script files are generated:

  • Hd_tb_compile.do : Mentor Graphics ModelSim compilation script. This script contains commands to compile the generated filter and test bench code.

  • Hd_tb_sim.do: Mentor Graphics ModelSim simulation script. This script contains commands to run a simulation of the generated filter and test bench code.

• Forces clock, clock enable, and reset input signals.

• Forces clock enable and reset input to active high.

• Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.

• Forces reset signals.

• Applies a hold time of 2 nanoseconds to filter reset and data input signals.

• For HDL test benches, applies an error margin of 4 bits.

Default Settings for Files

• Places generated files in the target folder hdlsrc and names the files as follows:

  File	Name
  Verilog source	Hd.v, where Hd is the name of the specified filter object
  VHDL source	Hd.vhd, where Hd is the name of the specified filter object
  VHDL package	Hd_pkg.vhd, where Hd is the name of the specified filter object

• Places generated files in a subfolder name hdlsrc, under your current working folder.

• Includes VHDL entity and architecture code in a single source file.

Default Settings for Register Resets

• Uses an asynchronous reset when generating HDL code for registers.

• Asserts the reset input signal high (1) to reset registers in the design.

Default Settings for General HDL Code

• Names the generated VHDL entity or Verilog module with the name of the filter.

• Names the filter's HDL ports as follows:

  HDL Port	Name
  Input	filter_in
  Output	filter_out
  Clock input	clk
  Clock enable input	clk_enable
  Reset input	reset

• Sets the data type for clock input, clock enable input, and reset ports to STD_LOGIC and data input and output ports to VHDL type STD_LOGIC_VECTOR or Verilog type wire.

• Names coefficients as follows:

  For...	Names Coefficients...
  FIR filters	coeffn, where n is the coefficient number, starting with 1
  IIR filters	coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number

• When declaring signals of type REAL, initializes the signal with a value of 0.0.

• Places VHDL configurations in any file that instantiates a component.

• Appends _rsvd to names that are VHDL or Verilog reserved words.

• Uses a type safe representation when concatenating zeros: '0' & '0'...

• Applies the statement IF clock'event AND clock='1' THEN to check for clock events.

• Allows scale values to be up to 3 bits smaller than filter input values.

• Adds an extra input register and an extra output register to the filter.

• Appends _process to process names.

• When creating labels for VHDL GENERATE statements:

  • Appends _gen to section and block names.

  • Names output assignment blocks with the string outputgen

Default Settings for Code Optimizations

• Generates HDL code that is bit-true to the original filter function and is not optimized for performance or space requirements.

• Applies a linear final summation to FIR filters. This form of summation is explained in most DSP text books.

• Enables multiplier operations for a filter, as opposed to replacing them with additions of partial products.

generatetb(Hd 'TbType', 'PropertyName', 'PropertyValue',...) generates an HDL test bench of a specified type to verify the HDL code generated for the quantized filter identified by Hd, using the specified property name and property value pair settings. You can specify the function with one or more of the property name and property value pairs described in Property Reference, and Properties — Alphabetical List.

generatetb(Hd) generates an HDL test bench to verify the HDL code generated for the quantized filter identified by Hd. . The 'TbType' argument is omitted, and the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or 'Verilog').

generatetb(Hd, 'PropertyName', 'PropertyValue',...) generates an HDL test bench to verify the HDL code generated for the quantized filter identified by Hd, using the specified property name and property value pair settings. The 'TbType' argument is omitted, and the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or 'Verilog').

You can specify the function with one or more of the property name and property value pairs described in Property Reference, and Properties — Alphabetical List.

Examples

1. Design a filter. The call to fdesign in the following command-line sequence designs a minimum order lowpass filter with a normalized passband frequency of 0.2, a stopband frequency of 0.22, a passband ripple of 1 dB, and a stopband attenuation of 60 dB.

2. Construct a filter object. The call to design constructs the FIR equiripple filter object Hd.

3. Set the filter arithmetic. The arithmetic assignment statement sets the filter arithmetic to fixed-point arithmetic.

4. Generate VHDL code for the filter. The call to generatehdl generates VHDL code for the filter Hd. The function names the file MyFilter.vhd and places it in the default target folder hdlsrc.

5. Generate a test bench for the filter. The call to generatetb generates a VHDL test bench for the filter Hd named MyFilterTB.vhd and places the generated test bench file in the default target folder hdlsrc.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2, 0.22, 1, 60);
Hd = design(d, 'equiripple');      % Create  FIR equiripple filter
Hd.arithmetic='fixed'; %Quantized filter with default settings
generatehdl(Hd, 'Name', 'MyFilter'); %Generate filter's VHDL code
generatetb(Hd, 'VHDL', 'TestBenchName', 'MyFilterTB');

How To

• generatetbstimulus
• generatehdl

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