User's Guide

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Getting Started	Introduces the product and gets you started using it
HDL Filter Code Generation Essentials	How to start an HDL code generation session for a filter, select VHDL or Verilog code generation, and apply and save HDL code generation settings
HDL Code for Supported Filter Structures	How to configure HDL code generation options that apply to specific filter structures .
Optimization of HDL Filter Code	: How to optimize HDL code generated for a filter with respect to resource usage, clock speed, chip area, or latency
Customization of HDL Filter Code	How to generate HDL filter code that conforms to your organization's HDL coding conventions and requirements
Verification of Generated HDL Filter Code	How to verify HDL code generated for a filter using Mentor Graphics ModelSim and Cadence Incisive
Synthesis and Workflow Automation	How to synthesize HDL filter code using FPGA synthesis tools such as such as Altera Quartus II, Mentor Graphics Precision, Synopsys Synplify Pro, and Xilinx ISE

Examples

HDL Filter Code Generation Essentials

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