InputType - Specify HDL data type for filter's input port

Settings

'std_logic_vector'

Specifies VHDL type STD_LOGIC_VECTOR for the filter input port.

'signed/unsigned'

Specifies VHDL type SIGNED or UNSIGNED for the filter input port.

'wire' (Verilog)

If the target language is Verilog, the data type for all ports is wire. This property is not modifiable in this case.

See Also

ClockEnableInputPort, ClockInputPort, InputPort, OutputPort, OutputType, ResetInputPort

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