MultifileTestBench - Divide generated test bench into helper functions, data, and HDL test bench code files

Settings

'on'

Write separate files for test bench code, helper functions, and test bench data. The file names are derived from the test bench name and the TestBenchDataPostfix property as follows:

TestBenchName_TestBenchDataPostfix

For example, if the test bench name is my_fir_filt, and the target language is VHDL, the default test bench file names are:

• my_fir_filt_tb.vhd: test bench code

• my_fir_filt_tb_pkg.vhd: helper functions package

• my_fir_filt_tb_data.vhd: test vector data package

If the test bench name is my_fir_filt and the target language is Verilog, the default test bench file names are:

• my_fir_filt_tb.v: test bench code

• my_fir_filt_tb_pkg.v: helper functions package

• my_fir_filt_tb_data.v: test bench data

'off' (default)

Write a single test bench file containing all HDL test bench code and helper functions and test bench data.

See Also

TestBenchName, TestBenchDataPostFix

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