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R2012a Documentation → Filter Design HDL Coder
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Contents

Index

• Getting Started

Automated HDL Code Generation

Filter Design HDL Coder Features and Components

Checking Product Requirements

Installing the Software

Using "What's This?" Context-Sensitive Help

Using Demos and Tutorials

Creating a Folder for Your Tutorial Files

Basic FIR Filter

Optimized FIR Filter

• User's Guide

• Release Notes

Summary by Version

Version 2.9.1 (R2012a) Filter Design HDL Coder Software

Version 2.9 (R2011b) Filter Design HDL Coder Software

Version 2.8 (R2011a) Filter Design HDL Coder Software

Version 2.7 (R2010b) Filter Design HDL Coder Software

Version 2.6 (R2010a) Filter Design HDL Coder Software

Version 2.5 (R2009b) Filter Design HDL Coder Software

Version 2.4 (R2009a) Filter Design HDL Coder Software

Version 2.3 (R2008b) Filter Design HDL Coder Software

Version 2.2 (R2008a) Filter Design HDL Coder Software

Compatibility Summary for Filter Design HDL Coder Software

MultiplierOutputPipeline - Specify number of pipeline stages at multiplier outputs for FIR filters

Settings

nStages

Default: 0. nStages must be an integer greater than or equal to 0.

MultiplierOutputPipeline lets you specify generation of pipeline stages at multiplier outputs for all FIR filter structures. Multiplier pipelining can help you achieve significantly higher clock rates.

Usage Notes

The coder ignores this property if CoeffMultipliers is not set to 'multipliers'.

See Also

CoeffMultipliers

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