OutputType - Specify HDL data type for filter's output port

Settings

'Same as input data type' (VHDL default)

The filter's output port has the same type as the specified input port type.

'std_logic_vector'

The filter's output port has VHDL type STD_LOGIC_VECTOR.

'signed/unsigned'

The filter's input port has type SIGNED or UNSIGNED.

'wire' (Verilog)

If the target language is Verilog, the data type for all ports is wire. This property is not modifiable in this case.

See Also

ClockEnableInputPort, ClockInputPort, InputPort, InputType, OutputPort, ResetInputPort

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