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| R2012a Documentation → Filter Design HDL Coder | |
Learn more about Filter Design HDL Coder |
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| Contents | Index |
This table summarizes what's new in Version 2.8 (R2011a)
| New Features and Changes | Version Compatibility Considerations | Fixed Bugs and Known Problems |
|---|---|---|
| Yes Details below | Yes—Details labeled as Compatibility Considerations, below. See also Summary. | No |
New features and changes introduced in this version are:
Distributed Arithmetic and Serial Architectures Supported for Cascaded Filters
Support for Partly Serial Architecture for FIR Interpolators
The coder now supports Distributed Arithmetic (DA) and serial architectures for cascade filters. You can use this feature only with the command-line interface (generatehdl). See Architecture Options for Cascaded Filters for more details and some examples.
R2011a removes the generatetb function. To generate a test bench for your HDL filter code, you should instead use the generatehdl function. Set the GenerateHDLTestbench property to 'on', as shown in the following example.
generatehdl(Hlp, 'GenerateHDLTestbench', 'on');
See the GenerateHDLTestbench reference page for details.
In Release R2011a, the generatetb function will continue to operate, but it will display a warning message when called.
You should replace all calls to generatetb in your scripts with calls to generatehdl. When you do so, enable test bench generation with the GenerateHDLTestbench property, as shown in the preceding example.
See also Enabling Test Bench Generation.
Effective with R2011a, you can specify a partly or fully serial architecture for IIR SOS filter structures. At this time, Filter Design HDL Coder supports only Direct Form I SOS filters (df1sos).
You can specify serial architecture using generatehdl or through the Generate HDL dialog box (on the Filter Architecture tab). For more details, see Serial Architectures for IIR SOS Filters and Specifying Serial Architectures for IIR SOS Filters.
Effective with R2011a, you can specify a partly serial architecture for FIR interpolator filters (mfilt.firinterp ). See Speed vs. Area Optimizations for HDL Filter Realizations for detailed information about parallel and serial architectures supported for HDL code generation.
The Synthesis script options in the EDA Tool Scripts pane now includes the options Choose synthesis tool and Synthesis file postfix.
These options let you specify generation of a tool-specific synthesis script. See Automation Scripts for Third-Party Synthesis Tools for details.
 | Version 2.9 (R2011b) Filter Design HDL Coder Software | Version 2.7 (R2010b) Filter Design HDL Coder Software |  |
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