TestBenchClockEnableDelay - Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable

Settings

N (integer number of clock cycles) Default: 1

The TestBenchClockEnableDelay property specifies a delay time N, expressed in clock cycles (the default value is 1) elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. TestBenchClockEnableDelay works in conjunction with the HoldTime property. After deassertion of reset, the clock enable goes high after a delay of N clock cycles plus the delay specified by HoldTime.

In the figure below, the reset signal (active-high) deasserts after the interval labeled Hold Time. The clock enable asserts after a further interval labeled Clock enable delay.

See Also

HoldTime, ResetLength

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