UseVerilogTimescale - Allow or exclude use of compiler ˋtimescale directives in generated Verilog code

Settings

'on' (default)

Use compiler ˋtimescale directives in generated Verilog code.

'off'

Suppress the use of compiler ˋtimescale directives in generated Verilog code.

Usage Notes

The ˋtimescale directive provides a way of specifying different delay values for multiple modules in a Verilog file.

See Also

CastBeforeSum, InlineConfigurations, LoopUnrolling, SafeZeroConcat, UseAggregatesForConst, UseRisingEdge

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