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Error Caused by Signal-Based Event Cycle |
This example shows how to eliminate an event-based signal cycle using the following resolution techniques. A signal-based event cycle is a loop formed by blocks that unconditionally update their outputs in response to a signal-based event. Such a cycle can cause an infinite loop during a simulation.
Error Caused by Signal-Based Event Cycle
Simulating the following model (open model) causes an error because of a signal-based event cycle. If the simulation proceeds, a sample time hit of the #d signal causes the following actions to repeat in an infinite loop:
The Add block executes because of a sample time hit of one of its input signals.
The Gain, Bias, Signal Scope, and Gain1 blocks execute.

Resolution Using Atomic Subsystem and Unit Delay Blocks
The following model (open model) performs the computation in an Atomic Subsystem block, and includes a Unit Delay block on a signal line that connects to an input port of the Add block. During the simulation, a sample time hit of the #d signal causes the subsystem to execute. The subsystem executes each block inside the subsystem exactly once. The output of the Unit Delay block is the same as the output of the Gain1 block from the previous invocation of the subsystem.



Alternative Resolution Using Signal Latch Block
The following model (open model) includes a Signal Latch block on a signal line that connects to the Add block. As a result, a sample time hit of the #d signal causes the following actions to occur once:
The Add block executes because of a sample time hit of its first input signal.
The Gain, Bias, Signal Scope, and Gain1 blocks execute.
The sample time hit at the rts port of the Signal Latch block causes an update in the out output signal. The value of this signal is the same as the output of the Gain1 block from the previous time this entire sequence of actions occurred.
The Add block executes again because of a sample time hit of its second input signal.
The Gain, Bias, Signal Scope, and Gain1 blocks execute again.
The two sample time hits at the wts port of the Signal Latch block cause the block to write the value of the in input signal to the block memory. This operation does not cause the block to update the out output signal.


![]() | Livelock Prevention | Notifications and Queries Among Blocks | ![]() |

Model electronic system architectures, process flows, and logistics as queuing systems or agent-based systems.
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