Unit Delay Resettable - Delay signal one sample period, with external Boolean reset

Library

Additional Math & Discrete / Additional Discrete

Description

The Unit Delay Resettable block delays a signal one sample period.

The block can reset both its state and output based on an external reset signal R. The block has two input ports, one for the input signal u and the other for the external reset signal R.

At the start of simulation, the block's Initial condition parameter determines its initial output. During simulation, when the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state and its output to the Initial condition.

You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.

Data Type Support

The Unit Delay Resettable block accepts signals of the following data types:

Floating point
Built-in integer
Fixed point
Boolean
Enumerated

The output has the same data type as the input u. For enumerated signals, the Initial condition must be of the same enumerated type as the input u.

For more information, see Data Types Supported by Simulink in the Simulink documentation.

Parameters and Dialog Box

Initial condition: Specify the initial output of the simulation.
Sample time: Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See How to Specify the Sample Time in the online documentation for more information.

Characteristics

Direct Feedthrough	No, of the input port Yes, of the reset port
Sample Time	Specified in the Sample time parameter
Scalar Expansion	Yes
Zero-Crossing Detection	No