Key Features

  What You Need to Know

  Required Products

  About This Demo

  Opening the Model

  Generating Test Cases

  Combining Test Cases

  Example: Analyzing an Atomic Subchart Using the Simulink Design Verifier Software

  Next Step

  Product Help

  MathWorks Online

  Analyzing a Model Using the Simulink Design Verifier Software

  Analyzing a Simple Model

  Analyzing Model Blocks

  Block Reduction

  Inline Parameters

  Analyzing Large Models

• Handling Incompatibilities with Automatic Stubbing

  Handling Nonfinite Data

• Approximations

  Short-Circuiting Logic Blocks

• Checking Model Compatibility

  Unsupported Simulink Software Features

  Simulink Block Support Limitations

  Limitations of Support for Model Blocks

• Unsupported Stateflow Software Features

• Support Limitations for MATLAB for Code Generation

  Fixed-Point Support Limitations

  About Block Replacements

  Built-In Block Replacements

  Template for Block Replacement Rules

• Defining Custom Block Replacements

• Executing Block Replacements

  About Parameter Configurations

• Defining Parameter Configurations

• Parameter Configuration Example

  What Is Design Error Detection?

  Derived Ranges in Design Error Detection

• Running a Design Error Detection Analysis

• Detecting Dead Logic

• Detecting Integer Overflow and Division-by-Zero Errors

• Checking for Specified Intermediate Minimum and Maximum Signal Values

• About Test Case Generation

  Workflow for Generating Test Cases

• Generating Test Cases to Achieve Decision Coverage for a Model

  Generating Test Cases for a Subsystem

  When to Extend Existing Test Cases

  Common Workflow for Extending Existing Test Cases

• Example: Extending Existing Test Cases for a Model that Uses Temporal Logic

• Example: Extending Existing Test Cases for a Closed-Loop System

• Example: Extending Existing Test Cases for a Modified Model

  Generating Test Cases for Missing Coverage Data

• Example: Achieving Missing Coverage in a Referenced Model

  Achieving Missing Coverage for Subsystems and Model Blocks

• Example: Achieving Missing Coverage in a Closed-Loop Simulation Model

• What Is Component Verification?

  Functions for Component Verification

• Example: Verifying a Component for Code Generation

• Overview

  Example: Output Minimum and Maximum Values on Inport Blocks

  sldvData Fields for Minimum and Maximum Input Values

  Example: Minimum and Maximum Values in Simulink.Signal Objects

  Example: Minimum and Maximum Values on Stateflow Data Objects

  Example: Minimum and Maximum Values in Subsystems

  Example: Minimum and Maximum Values in Global Data Storage

• About Property Proving

  Workflow for Proving Model Properties

• Proving Properties in a Model

• Using a Verification Model to Prove System-Level Properties

  Proving Properties in a Subsystem

• Property-Proving Examples

• Highlighted Results on the Model

• Simulink Design Verifier Data Files

• Harness Model

  SystemTest TEST-Files

• Simulink Design Verifier Reports

  Simulink Design Verifier Log Files

  Reviewing Analysis Results in the Model Explorer

  Sources of Model Complexity

• Analyzing a Large Model

  Generating Reports for Large Models

• Managing Model Data to Simplify the Analysis

  Partitioning Model Inputs and Generating Tests Incrementally

  Analyzing the Model Using a Bottom-Up Approach

• Extracting Subsystems for Analysis

  Analyzing Logical Operations

  Handling Models with Large State Spaces

  Handling Problems with Counters and Timers

• Techniques for Proving Properties of Large Models

  Overview of Simulink Design Verifier Configuration Parameters

• Design Verifier Pane

• Design Verifier Pane: Block Replacements

• Design Verifier Pane: Parameters

• Design Verifier Pane: Test Generation

• Design Verifier Pane: Design Error Detection

• Design Verifier Pane: Property Proving

• Design Verifier Pane: Results

• Design Verifier Pane: Report

  Parameter Command-Line Information Summary

  Overview of Simulink Block Support

  Additional Math and Discrete Library

  Commonly Used Blocks Library

  Continuous Library

  Discontinuities Library

  Discrete Library

  Logic and Bit Operations Library

  Lookup Tables Library

  Math Operations Library

  Model Verification Library

  Model-Wide Utilities Library

  Ports & Subsystems Library

  Signal Attributes Library

  Signal Routing Library

  Sinks Library

  Sources Library

  User-Defined Functions Library