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| R2012a Documentation → Simulink Design Verifier | |
Learn more about Simulink Design Verifier |
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| Contents | Index |
Block Reference |  Alphabetical List |
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| Proof Assumption | Constrain signal values when proving model properties |
| Proof Objective | Define objectives that signals must satisfy when proving model properties |
| Test Condition | Constrain signal values in test cases |
| Test Objective | Define custom objectives that signals must satisfy in test cases |
| Detector | Detect true duration on input and construct output true duration based on output type |
| Extender | Extend true duration of input |
| Within Implies | Capture within implication if observed input is true within each true duration of first input |
| Implies | Specify conditions that produce certain responses |
| Verification Subsystem | Represent subsystem that specifies proof or test objectives without impacting simulation results or generated code |
 | Functions — Alphabetical List | Blocks — Alphabetical List |  |
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
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