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Automatic stubbing lets you analyze a model that contains objects that the Simulink Design Verifier software does not support.
When you enable the automatic stubbing option (it is enabled by default), the software considers only the interface of the unsupported objects, not their actual behavior. This technique allows the software to complete the analysis. However, the analysis may achieve only partial results if any unsupported model element affects the simulation outcome.
If you enable automatic stubbing, when the Simulink Design Verifier analysis comes to an unsupported block, the software "stubs" that block. The analysis ignores the behavior of the block, and as a result, the block output can take any value.
The Simulink Design Verifier software does not support Trigonometric Function blocks when the Function parameter is set to acos, such as the one in the following graphic.

When stubbing this block during analysis, out_signal can take any value, with the following results.
| Analysis Model | Result of Stubbing out_signal |
|---|---|
Design error detection |
|
Test case generation |
|
Property proving |
|
The Simulink demo model sfcndemo_sfun_fcncall has an S-Function block. The S-function sfun_fcncall triggers the execution of the function-call subsystems f1 subsys1 and f2 subsys2 on the first and second elements of the first output port.

The Simulink Design Verifier software does not support the S-Function block, so if automatic stubbing is enabled, the analysis ignores the behavior of the S-function. As a result, the code that triggers the two function-call subsystems is ignored, resulting in two unsatisfiable objectives. Since the function calls are ignored, the contents of those subsystems are effectively eliminated from the analysis.
This section describes a workflow for using automatic stubbing, with a simple Simulink model as an example.
The following model contains a Trigonometric Function block that is not compatible with the Simulink Design Verifier software.

From the Model Editor, there are two ways to check whether a model is compatible with the Simulink Design Verifier software:
Run the Simulink Design Verifier compatibility check by selecting Tools > Design Verifier > Check Model Compatibility.

Select the analysis that you want:
Tools > Design Verifier > Detect Design Errors
Tools > Design Verifier > Generate Tests
Tools > Design Verifier > Prove Properties
The software first checks the compatibility of the model. If the model itself is incompatible, for example, if it uses a variable-step solver, the analysis cannot continue.
If it finds incompatible elements in the model, the software analyzes the model, and by default, stubs out the incompatible elements. The Simulation Diagnostics Viewer also opens, listing the incompatibilities.

Note For more information, see Simulation Diagnostics Viewer. |
Automatic stubbing is enabled by default. To change the automatic stubbing setting, in the Configuration Parameters dialog box, on the main Design Verifier pane, select Automatic stubbing of unsupported block and functions. When you run the analysis, the software tells you that stubbing is turned on and the analysis continues.
If you run an analysis with automatic stubbing enabled, make sure to review the results. In this report, generated after a test case generation analysis, you see a table of unsupported blocks that the software encountered.

The Summary report for the example model shows that one objective was satisfied without generating a test case. The software cannot generate the test case because it does not understand the operation of the Trigonometric Function block.

If your analysis does not achieve complete results because of the stubbing, you can define custom block replacements to give a more precise definition of the unsupported blocks. For more information:
See
At the MATLAB command line, enter
echodemo sldvdemo_blockreplacement_unsupportedblocks
to step through the "Block Replacements for Unsupported Blocks" demo.
![]() | Analyzing Large Models | Handling Nonfinite Data | ![]() |

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