Properties — Alphabetical List

By Category

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BalanceDelays
BlockGenerateLabel
CastBeforeSum
CheckHDL
ClockEnableInputPort
ClockEnableOutputPort
ClockHighTime
ClockInputs
ClockInputPort
ClockLowTime
ClockProcessPostfix
CodeGenerationOutput
ComplexImagPostfix
ComplexRealPostfix
DateComment
EDAScriptGeneration
EnablePrefix
EntityConflictPostfix
ForceClock
ForceClockEnable
ForceReset
GenerateCoSimBlock
GenerateCoSimModel
Generatedmodelname
Generatedmodelnameprefix
GenerateHDLCode
GenerateValidationModel
HandleAtomicSubsystem
HDLCompileInit
HDLCompileTerm
HDLCompileFilePostfix
HDLCompileVerilogCmd
HDLCompileVHDLCmd
HDLControlFiles
HDLMapPostfix
HDLSimCmd
HDLSimInit
HDLSimFilePostfix
HDLSimTerm
HDLSimViewWaveCmd
HDLSynthCmd
HDLSynthFilePostfix
HDLSynthInit
HDLSynthTerm
HDLSynthTool
HierarchicalDistPipelining
Highlightancestors
Highlightcolor
HoldInputDataBetweenSamples
HoldTime
IgnoreDataChecking
InitializeBlockRAM
InitializeTestBenchInputs
InlineConfigurations
InlineMATLABBlockCode
InputType
InstanceGenerateLabel
InstancePostfix
InstancePrefix
LoopUnrolling
MaskParameterAsGeneric
MinimizeClockEnables
MinimizeIntermediateSignals
MulticyclePathInfo
MultifileTestBench
OptimizationReport
OptimizeTimingController
OutputGenerateLabel
OutputType
Oversampling
PackagePostfix
PipelinePostfix
RAMMappingThreshold
RequirementComments
ReservedWordPostfix
ResetAssertedLevel
ResetInputPort
ResetLength
ResetType
ResetValue
ResourceReport
SafeZeroConcat
ScalarizePorts
SimulatorFlags
SplitArchFilePostfix
SplitEntityArch
SplitEntityFilePostfix
TargetDirectory
TargetLanguage
TestBenchClockEnableDelay
TestBenchDataPostFix
TestBenchPostFix
TimingControllerPostfix
TestBenchReferencePostFix
Traceability
UseAggregatesForConst
UserComment
UseRisingEdge
UseVerilogTimescale
VectorPrefix
Verbosity
VerilogFileExtension
VHDLArchitectureName
VHDLFileExtension
VHDLLibraryName

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