Overview of Multirate Models

The coder supports HDL code generation for single-clock and multiple clock multirate models. Your model can include blocks running at multiple sample rates:

• Within the device under test (DUT).

• In the test bench driving the DUT. In this case, the DUT inherits multiple sample rates from its inputs or outputs.

• In both the test bench and the DUT.

A timing controller entity generates the required rates from a single master clock using one or more counters, creating multiple clock enables. The master clock rate is the fastest rate in the model in single clock mode. In multiple clock mode, it can be any clock in the DUT. The outputs of the timing controller are clock enable signals running at rates an integer multiple slower than the timing controller's master clock

Each timing controller entity definition is written to a separate code file. The timing controller file and entity names derive from the name of the subsystem that is selected for code generation (the DUT). To form the timing controller name, the coder appends the value of the TimingControllerPostfix property to the DUT name.

When using single clock mode, HDL code generated from multirate models employs a single master clock that corresponds to the base rate of the DUT. When using multiple clock mode, HDL code generated from multirate models employs one clock input for each rate in the DUT. The number of timing controllers generated in multiple clock mode depends on the design in the DUT.

In general, generating HDL code for a multirate model does not differ greatly from generating HDL code for a single-rate model. However, there are a few requirements and restrictions on the configuration of the model and the use of specialized blocks (such as Rate Transitions) that apply to multirate models. These are discussed in the following sections.

Generating HDL Code for Multirate Models

Configuring Multirate Models for HDL Code Generation

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