Generating HDL Code Using the GUI

Simulink HDL Coder GUI Overview

You can view and edit options and parameters that affect HDL code generation in the Configuration Parameters dialog box, or in the Model Explorer.

The following figure shows the top-level HDL Code Generation pane in the Configuration Parameters dialog box.

The following figure shows the top-level HDL Code Generation options pane in the Model Explorer.

If you are not familiar with Simulink configuration sets, or how to view and edit them in the Configuration Parameters dialog box, see the following documentation:

• Manage a Configuration Set

• Configuration Parameters Dialog Box

If you are not familiar with the Model Explorer, see Exploring, Searching, and Browsing Models.

In the hands-on code generation exercises that follow, you use the Configuration Parameters dialog box to view and set the coder options and controls. The exercises use the sfir_fixed model (see The sfir_fixed Model) in basic code generation and verification steps.

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Creating a Folder and Local Model File

In this section you will setup the folder and a local copy of the demo model.

Creating a Folder

Start by setting up a working folder:

1. Start MATLAB.

2. Create a folder named sl_hdlcoder_work, for example:

   mkdir C:\work\sl_hdlcoder_work
   

   You will use sl_hdlcoder_work to store a local copy of the demo model and to store folders and code generated by the coder. The location of the folder does not matter, except that it should not be within the MATLAB folder tree.

3. Make the sl_hdlcoder_work folder your working folder, for example:

   cd C:\work\sl_hdlcoder_work
   

Making a Local Copy of the Model File

Next, make a copy of the sfir_fixed model:

1. To open the model, type the following command at the MATLAB prompt:

   sfir_fixed
   

2. Save a local copy of sfir_fixed.mdl to your working folder.

3. Leave the sfir_fixed model open and proceed to the next section.

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Viewing Coder Options in the Configuration Parameters Dialog Box

The coder option settings are displayed as a category of the model's active configuration set. You can view and edit these options in the Configuration Parameters dialog box, or in the Model Explorer. This discussion uses the Configuration Parameters dialog box.

To access the coder settings:

1. Open the Configuration Parameters dialog box.

2. Select the HDL Code Generation pane.

   

   The HDL Code Generation pane contains top-level options and buttons that control the HDL code generation process. Several other categories of options are available under the HDL Code Generation entry in the Select tree. This exercise uses a small subset of these options, leaving the others at their default settings.

   Code Generation Options in the Simulink HDL Coder Dialog Boxes summarizes all the options available in the HDL Code Generation category.

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Initializing Model Parameters with hdlsetup

Before generating code, you must set some parameters of the model. Rather than doing this manually, use the hdlsetup command. The hdlsetup command uses the set_param function to set up models for HDL code generation quickly and consistently.

To set the model parameters:

1. At the MATLAB command prompt, type:

   hdlsetup('sfir_fixed')
   

2. Save the model with its new settings.

Before continuing with code generation, consider the settings that hdlsetup applies to the model.

hdlsetup configures Solver options that are recommended or required by the coder. These options are:

• Type: Fixed-step. (The coder currently supports variable-step solvers under limited conditions. See hdlsetup.)

• Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the correct one for simulating discrete systems.

• Tasking mode: SingleTasking. The coder does not currently support models that execute in multitasking mode.

  Do not set Tasking mode to Auto.

hdlsetup also configures the model start and stop times and fixed-step size as follows:

• Start Time: 0.0 s

• Stop Time: 10 s

• Fixed step size (fundamental periodic sample time): auto

If Fixed step size is set to auto the step size is chosen automatically, based on the sample times specified in the model. In the demo model, only the Signal From Workspace block specifies an explicit sample time (1 s); all other blocks inherit this sample time.

The model start and stop times determine the total simulation time. This in turn determines the size of data arrays that are generated to provide stimulus and output data for generated test benches. For the demo model, computation of 10 seconds of test data does not take a significant amount of time. Computation of sample values for more complex models can be time consuming. In such cases, you may want to decrease the total simulation time.

The remaining parameters set by hdlsetup affect error severity levels, data logging, and model display options. If you want to view the complete set of model parameters affected by hdlsetup, open hdlsetup.m in the MATLAB Editor.

The model parameter settings provided by hdlsetup are intended as useful defaults, but they may not be appropriate for all your applications. For example, hdlsetup sets a default Simulation stop time of 10 s. A total simulation time of 1000 s would be more realistic for a test of the sfir_fixed demo model. If you would like to change the simulation time, enter the desired value into the Simulation stop time field of the Simulink Editor.

See the "Model Parameters" table in the "Model and Block Parameters" section of the Simulink documentation for a summary of user-settable model parameters.

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Selecting and Checking a Subsystem for HDL Compatibility

The coder generates code from either the current model or from a subsystem at the root level of the current model. You use the Generate HDL for menu to select the model or subsystem from which code is to be generated. Each entry in the menu shows the full path to the model or one of its subcomponents.

The sfir_fixed model is configured with the sfir_fixed/symmetric_fir subsystem selected for code generation. If this is not the case, make sure that the symmetric_fir subsystem is selected for code generation, as follows:

1. Select sfir_fixed/symmetric_fir from the Generate HDL for menu.

2. Click Apply.

To check HDL compatibility for the subsystem:

1. Click the Run Compatibility Checker button.

2. The HDL compatibility checker examines the system selected in the Generate HDL for menu for any compatibility problems. In this case, the selected subsystem is fully HDL-compatible, and the compatibility checker displays the following message:

   ### Starting HDL Check.
   ### HDL Check Complete with 0 errors, warnings and messages.
   

3. The compatibility checker also displays an HTML report in a Web browser, as shown in the following figure.

   

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Generating VHDL Code

The top-level HDL Code Generation options are now set as follows:

• The Generate HDL for field specifies the sfir_fixed/symmetric_fir subsystem for code generation.

• The Language field specifies (by default) generation of VHDL code.

• The Folder field specifies a target folder that stores generated code files and scripts. The default target folder is a subfolder of your working folder, named hdlsrc.

Before generating code, select Current Folder from the Desktop menu in the MATLAB window. This displays the Current Folder browser, which lets you access your working folder and the files that will be generated within it.

To generate code:

1. Click the Generate button.

2. As code generation proceeds, the coder displays progress messages. The process should complete successfully with the message

   ### HDL Code Generation Complete.
   

   Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.

   The coder compiles the model before generating code. Depending on model display options (such as port data types, etc.), the appearance of the model may change after code generation.

3. A folder icon for the hdlsrc folder is now visible in the Current Folder browser. To view generated code and script files, double-click the hdlsrc folder icon.

4. The files that were generated in the hdlsrc folder are:

   • symmetric_fir.vhd: VHDL code. This file contains an entity definition and RTL architecture implementing the symmetric_fir filter.

   • symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vcom command) to compile the generated VHDL code.

   • symmetric_fir_synplify.tcl: Synplify synthesis script.

   • symmetric_fir_map.txt: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Code Tracing Using the Mapping File).

5. To view the generated VHDL code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser.

   At this point it is suggested that you study the ENTITY and ARCHITECTURE definitions while referring to HDL Code Generation Defaults in the makehdl reference documentation. The reference documentation describes the default naming conventions and correspondences between the elements of a model (subsystems, ports, signals, etc.) and elements of generated HDL code.

6. Before proceeding to the next section, close any files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.

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Generating VHDL Test Bench Code

At this point, the Generate HDL for, Language, and Folder fields are set as they were in the previous section. Accordingly, you can now generate VHDL test bench code to drive the VHDL code generated previously for the sfir_fixed/symmetric_fir subsystem. The code will be written to the same target folder as before.

To generate a VHDL test bench:

1. Select the HDL Code Generation > Test Bench pane.

   

2. Select HDL test bench.

3. Click the Generate Test Bench button.

4. As test bench generation proceeds, the coder displays progress messages. The process should complete successfully with the message

   ### HDL TestBench Generation Complete.
   

5. The generated files in the hdlsrc folder are:

   • symmetric_fir_tb.vhd: VHDL test bench code, with generated test and output data.

   • symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vcom commands). This script compiles and loads the entity to be tested (symmetric_fir.vhd) and the test bench code (symmetric_fir_tb.vhd).

   • symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.

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Verifying Generated Code

You can now take the generated code and test bench to an HDL simulator for simulated execution and verification of results. See Simulating and Verifying Generated HDL Code for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

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Generating Verilog Model and Test Bench Code

The procedure for generating Verilog code is the same as for generating VHDL code (see Generating a VHDL Entity from a Subsystem and Generating VHDL Test Bench Code), except that you select Verilog from the Language field of the HDL Code Generation options.

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Generating HDL Code Using the Command Line Interface

Simulating and Verifying Generated HDL Code

Related Products & Applications

• Simulink
• Control Design
• Signal Processing & Communications
• Model-Based Design
• Physical Modeling
• Verification & Validation

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