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Introduction to Stateflow HDL Code Generation

Overview

Stateflow charts provide concise descriptions of complex system behavior using hierarchical finite state machine (FSM) theory, flow diagram notation, and state-transition diagrams.

You use a chart to model a finite state machine or a complex control algorithm intended for realization as an ASIC or FPGA. When the model meets design requirements, you then generate HDL code (VHDL or Verilog) that implements the design embodied in the model. You can simulate and synthesize generated HDL code using industry standard tools, and then map your system designs into FPGAs and ASICs.

In general, generation of VHDL or Verilog code from a model containing a chart does not differ greatly from HDL code generation from any other model. The HDL code generator is designed to

Demos and Related Documentation

Demos

The following demos, illustrating HDL code generation from subsystems that include Stateflow charts, are available:

To open the demo models, type the following command:

 demos

This command opens the Help window. In the Demos pane on the left, select Simulink > Simulink HDL Coder. Then, double-click the icon for any of the following demos, and follow the instructions in the demo window.

Related Documentation

If you are familiar with Stateflow charts and Simulink models but have not yet tried HDL code generation, see the hands-on exercises in Introduction to HDL Code Generation.

If you are not familiar with Stateflow charts, see Stateflow Getting Started Guide. See also the Simulink® Coder™ documentation.

  


Related Products & Applications

Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.

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