The sfir_fixed Model

These exercises use the sfir_fixed model as a source for HDL code generation. The model simulates a symmetric finite impulse response (FIR) filter algorithm, implemented with fixed-point arithmetic. The following figure shows the top level of the model.

This model uses a division of labor that is helpful in HDL design:

• The symmetric_fir subsystem, which implements the filter algorithm, is the device under test (DUT). An HDL entity will be generated, tested, and eventually synthesized from this subsystem.

• The top-level model components that drive the subsystem work as a test bench.

The top-level model generates 16-bit fixed-point input signals for the symmetric_fir subsystem. The Signal From Workspace block generates a test input (stimulus) signal for the filter. The four Constant blocks provide filter coefficients.

The Scope blocks are used in simulation only. They are virtual blocks, and do not generate any HDL code.

The following figure shows the symmetric_fir subsystem.

Appropriate fixed-point data types propagate throughout the subsystem. Inputs inherit the data types of the signals presented to them. Where required, internal rules of the blocks determine the correct output data type, given the input data types and the operation performed (for example, the Product blocks).

The filter outputs a fixed-point result at the y_out port, and also replicates its input (after passing it through several delay stages) at the delayed_x_out port.

In the exercises that follow, you generate VHDL code that implements the symmetric_fir subsystem as an entity. You then generate a test bench from the top-level model. The test bench drives the generated entity, for the required number of clock steps, with stimulus data generated from the Signal From Workspace block.

Overview of Exercises

Generating HDL Code Using the Command Line Interface

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