Example: Latency

This example uses the simplevectorsum_cascade model. This model is identical to the model in the previous example (Example: Numeric Differences), except that it uses a cascaded implementation for the Sum block. This implementation introduces both latency and numeric differences.

The following figure shows the HDL Properties dialog box for a Sum block, with the Cascade implementation selected. This implementation generates a cascade of adders for the Sum block.

In the generated code, partial sums are computed by adders arranged in a cascade structure. Each adder computes a partial sum by demultiplexing and adding several inputs in succession. These computation take several clock cycles. On each cycle, an addition is performed; the result is then added to the next input.

To complete all computations within one sample period, the system master clock runs faster than the nominal sample rate of the system. A latency of one clock cycle (in the case of this model) is required to transmit the final result to the output. The inputs cannot change until all computations have been performed and the final result is presented at the output.

The generated HDL code runs at two effective rates: a faster rate for internal computations, and a slower rate for input/output. A special timing controller entity (vsum_tc) generates these rates from a single master clock using counters and multiple clock enables. The vsum_tc entity definition is written to a separate code file.

The generated model, gm_simplevectorsum_cascade, looks something like this:

As in the previous (gm_simplevectorsum) example, the vsum subsystem is highlighted in cyan. This highlighting indicates that the subsystem differs in some respect from the vsum subsystem of the original model.

The following block diagram shows the vsum subsystem in the generated model. The subsystem has been restructured to reflect the structure of the generated HDL code; inputs are grouped and routed to three adders for partial sum computations.

A Unit Delay (highlighted in cyan) has been inserted before the final output. This block delays (in this case, for one sample period) the appearance of the final sum at the output. The delay reflects the latency of the generated HDL code.

Note   The HDL code generated from the example model used in this section is bit-true to the original model. However, in some cases, cascaded block implementations can produce numeric differences between the original model and the generated HDL code, in addition to the introduction of latency. Numeric differences can arise from saturation and rounding operations.

Example: Numeric Differences

Defaults and Options for Generated Models

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