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| R2011b Documentation → Simulink HDL Coder | |
Learn more about Simulink HDL Coder |
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| Contents | Index |
Interface generation parameters let you customize port names and other attributes of interfaces generated for the following block types:
simulink/Ports & Subsystems/Model
built-in/Subsystem
lfilinklib/HDL Cosimulation
modelsimlib/HDL Cosimulation
The HDL Properties dialog box displays the interface generation parameters for these block types. The following dialog box shows the default settings for the BlackBox implementation for a Subsystem block.
The following table summarizes the names, value settings, and purpose of the interface generation parameters. All parameters have string data type.
| Parameter Name | Values | Description |
|---|---|---|
| AddClockEnablePort | 'on' | 'off' Default: 'on' | If 'on', add a clock enable input port to the interface generated for the block. The name of the port is specified by ClockEnableInputPort. |
| AddClockPort | 'on' | 'off' Default: 'on' | If 'on', add a clock input port to the interface generated for the block. The name of the port is specified by ClockInputPort. |
| AddResetPort | 'on' | 'off' Default: 'on' | If 'on', add a reset input port to the interface generated for the block. The name of the port is specified by ResetInputPort. |
| ClockEnableInputPort | Default: 'clk_enable' | Specifies HDL name for block's clock enable input port. |
| ClockInputPort | Default: 'clk' | Specifies HDL name for block's clock input signal. |
| EntityName | Default: Entity name is derived from the block name, modified if necessary to generate a legal VHDL entity name. | Specifies VHDL entity or Verilog module name generated for the block. |
| GenericList | Default: An empty cell array of string data. Each element of the cell array is another cell array of the form {'Name', 'Value', 'Type'}, where 'Type' is optional. If you omit 'Type', 'integer' is passed as the data type. | Specifies a list of parameter/value pairs (with optional data type specification) in string format to pass to a subsystem with a BlackBox implementation. |
| InlineConfigurations (VHDL only) | 'on' | 'off' Default: If this parameter is unspecified, defaults to the value of the global InlineConfigurations property. | If 'off', suppress generation of a configurations for the block, and require a user-supplied external configuration. |
| InputPipeline | Default: '0' | Specifies the number of input pipeline stages (pipeline depth) in the generated code. |
| OutputPipeline | Default: '0' | Specifies the number of output pipeline stages (pipeline depth) in the generated code. |
| ResetInputPort | Default: 'reset' | Specifies HDL name for block's reset input. |
| VHDLArchitectureName (VHDL only) | Default: 'rtl' | Specifies RTL architecture name generated for the block. The architecture name is generated only if InlineConfigurations = 'on'. |
| VHDLComponentLibrary (VHDL only) | Default: 'work' | Specifies the library from which to load the VHDL component. |
 | Generating a Simulink Model for Cosimulation with an HDL Simulator | Pass-Through and No-Op Implementations |  |
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