Limitation on Generated Verilog Interfaces

This section describes a limitation in the current release that applies to generation of Verilog interfaces for the following blocks:

• EDA Simulator Link HDL Cosimulation blocks

• Model block

When the target language is Verilog, only scalar ports are supported for code generation for these block types. Use of vector ports that are on these blocks will be reported as errors on the compatibility checker (checkhdl) report, and will raise a code generator (makehdl) error.

Pass-Through and No-Op Implementations

Stateflow HDL Code Generation Support

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