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| R2011b Documentation → Simulink HDL Coder | |
Learn more about Simulink HDL Coder |
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Defining the Counter Data Type and Size |
The HDL Counter block implements a free-running or count-limited hardware counter that supports signed and unsigned integer and fixed-point data types.
The counter emits its value for the current sample time from the count output. By default, the counter has no input ports. Optionally, you can add control ports that let you enable, disable, load, or reset the counter, or set the direction (positive or negative) of the counter.
The HDL Counter supports two operation modes, selected from the Counter type drop-down menu.
The counter is initialized to the value defined by the Initial value parameter upon assertion of a reset signal. The reset signal can be either the model's global reset, or a reset received through an optional Local reset port that you can define on the HDL Counter block.
On each sample time, the value defined by the Step value parameter is added to the counter, and the counter emits its current value at the count output. When the counter value overflows or underflows the counter's word size, the counter wraps around and continues the counting sequence until reset is asserted or the model stops running.
By default, the positive or negative direction of the count is determined by the sign of the Step value. Optionally, you can define a Count direction control port on the HDL Counter block.
Free Running Mode Examples. For a 4-bit unsigned integer counter with an Initial value of 0 and a Step value of 5, the counter output sequence is
0, 5, 10, 15, 4, 9,14,3,...
For a 4-bit signed integer counter with an Initial value of 0 and a Step value of -2, the counter output sequence is
0,-2,-4,-6,-8,6,4,2,0,-2,-4,...
The counter is initialized to the value defined by the Initial value parameter upon assertion of a reset signal. The reset signal can be either the model's global reset, or a reset received through an optional Local reset port that you can define on the HDL Counter block.
On each sample time, the value defined by the Step value parameter is added to the counter, and the current value is tested for equality with the value defined by the Count to value parameter. If the current value equals the Count to value, the counter is reloaded with the initial value. The counter then emits its current value at the count output.
If the counter value overflows or underflows the counter's word size, the counter wraps around and continues the counting sequence. The sequence continues until reset is asserted or the model stops running.
The condition for resetting the counter is exact equality. For some combinations of Initial value, Step value, and Count to value, the counter value may never equal the Count to value, or may overflow and iterate through the counter range some number of times before reaching the Count to value.
By default, the positive or negative direction of the count is determined by the sign of the Step value. Optionally, you can define a Count direction control port on the HDL Counter block.
Count Limited Mode Examples. For an 8-bit signed integer counter with an Initial value of 0, a Step value of 2, and a Count to value of 8, the counter output sequence is
0 2 4 6 8 0 ...
For a 3-bit unsigned integer counter with an Initial value of 0, a Step value of 3, and a Count to value of 7, the counter output sequence is
0 3 6 1 4 7 0 3 6 1 4 7 ...
For a 3-bit unsigned integer counter with an Initial value of 0, a Step value of 2, and a Count to value of 7, the counter output sequence never reaches the Count to value:
0 2 4 6 0 2 4 6 ...
By default, the HDL Counter has no inputs. Control ports are optional inputs that you can add to the block to:
Reset the counter independently from the global reset logic.
Load the counter with a value.
Enable or disable the counter.
Set the positive or negative direction of the counter.
The following figure shows the HDL Counter block configured with all available control ports.
The following characteristics apply to all control ports:
All control ports are synchronous.
All control ports except the load value input have Boolean data type.
All control ports must have the same sample time.
If any control ports exist on the block, the HDL Counter block inherits its sample time from the ports, and the Sample time parameter on the block dialog box is disabled.
All signals at control ports are active-high.
By default, the counter is loaded (or reloaded) with the defined Initial value at the following times:
When the model's global reset is asserted
(In Count limited mode only) When the counter value equals the Count to value
You can further control reset and load behavior with signals connected to control ports. You can add these control ports to the block via the following options:
Local reset port: Select this option to create a reset input port on the block. The local reset port is labeled rst. The rst port should be connected to a Boolean signal. When this signal is set to 1, the counter resets to its initial value.
Load ports: When you select this option, two input ports, labeled load and load_val, are created on the block. The load port should be connected to a Boolean signal. When this signal is set to 1, the counter is loaded with the value at the load_val input. The load value must have the same data type as the counter.
When you select the Count enable port option, a control port labeled enb is created on the block. The enb port should be connected to a Boolean signal. When this signal is set to 0, the counter is disabled and the current counter value is held at the output. When the enb signal is set to 1, the counter resumes operation.
By default, the negative or positive direction of the counter is determined by the sign of the Step value. When you select the Count direction port option, a control port labeled dir is created on the block. The dir port should be connected to a Boolean signal. The dir signal determines the direction of the counter as follows:
When the dir signal is set to 1, the step value is added to the current counter value to compute the next value.
When the dir signal is set to 0, the step value is subtracted from the current counter value to compute the next value.
In effect, when the signal at the dir port is 0, the counter reverses direction. The following table summarizes the effect of the Count direction port.
| Count Direction Signal Value | Step Value Sign | Actual Count Direction |
|---|---|---|
| 1 | + (Positive) | Up |
| 1 | - (Negative) | Down |
| 0 | + (Positive) | Down |
| 0 | - (Negative) | Up |
The following table defines the priority of control signals, and shows how the counter value is set in relation to the control signals.
| rst | load | enb | dir | Next Counter Value |
|---|---|---|---|---|
| 1 | – | – | – | initial value |
| 0 | 1 | – | – | load_val value |
| 0 | 0 | 0 | – | current value |
| 0 | 0 | 1 | 1 | current value + step value |
| 0 | 0 | 1 | 0 | current value - step value |
The HDL Counter block supports signed and unsigned integer and fixed-point data types. Use the following parameters to set the data type:
Output data type: Select Signed or Unsigned. The default is Unsigned.
Word length: Enter the desired number of bits (including the sign bit) for the counter.
Default: 8
Minimum: 1 if Output data type is Unsigned, 2 if Output data type is Signed
Maximum: 125
Fraction length: To define an integer counter, accept the default Fraction length of 0. To define a fixed-point counter, enter the number of bits to the right of the binary point.
Implementation: default
Implementation Parameters: InputPipeline, OutputPipeline
Counter type
Default: Free running
This drop-down menu selects the operation mode of the counter (see Counter Modes). The operation modes are:
Free running
Count limited
When Count limited is selected, the Count to value field is enabled.
Initial value
Default: 0
By default, the counter is loaded (or reloaded) with the defined Initial value at the following times:
When the model's global reset is asserted.
(In Count limited mode only) When the counter value equals the Count to value. See also Count Limited Mode.
Step value
Default: 1
The Step value is an increment that is added to the counter on each sample time. By default (i.e., in the absence of a count direction control signal) the sign of the step value determines the count direction (see also Controlling the Counter Direction).
Set Step value to a nonzero value that can be represented in the counter's data type precision without rounding. The magnitude (absolute value) of the step value must be a number that can be represented with the counter's data type.
For a signed N-bit integer counter:
The range of counter values is -(2N-1)..(2N-1 -1).
The range of legal step values is -(2N-1-1)..(2N-1 -1) (zero is excluded).
For example, for a 4-bit signed integer counter, the counter range is [-8..7], but the ranges of legal step values are [-7..-1] and [1..7].
Count to value
Default: 100
The Count to value field is enabled when the Count limited counter mode is selected. When the counter value is equal to the Count to value, the counter resets to the Initial value and continues counting. The condition for resetting the counter is exact equality. For some combinations of Initial value, Step value, and Count to value, the counter value may never equal the Count to value, or may overflow and iterate through the counter range some number of times before reaching the Count to value (see Count Limited Mode).
Set Count to value to a value that is not equal to the Initial value.
Local reset port
Default: cleared
Select this option to create a reset input port on the block. Only Boolean signals should be connected to this port. The port is labeled rst. See Creating Control Ports for Loading and Resetting the Counter.
Load ports
Default: cleared
Select this option to create load and load value input ports on the block. The ports are labeled load and load_val, respectively. The signal applied to the load port must be Boolean. The signal applied to the load_val port must have the same data type as the counter. See also Creating Control Ports for Loading and Resetting the Counter.
Count enable port
Default: cleared
Select this option to create a count enable input port on the block. Only Boolean signals should be connected to this port. The port is labeled enb. See also Enabling or Disabling the Counter.
Count direction port
Default: cleared
Select this option to create a count direction input port on the block. Only Boolean signals should be connected to this port. The port is labeled dir. See also Controlling the Counter Direction.
Counter output data is:
Default: Unsigned
This drop-down menu selects whether the counter output is signed or unsigned.
Word length
Default: 8
Word length is a positive integer that defines the size, in bits, of the counter.
Minimum: 1 if Output data type is Unsigned, 2 if Output data type is Signed
Maximum: 125
Fraction length
Default: 0
To define an integer counter, accept the default Fraction length of 0. To define a fixed-point counter, enter the number of bits to the right of the binary point.
Default: 0
Sample time
Default: 1
If the HDL Counter block has no input ports, the Sample time field is enabled, and an explicit sample time must be defined. Enter the desired sample time, or accept the default.
If the HDL Counter block has any input ports, this field is disabled, and the block sample time is inherited from the input signals. All input signals must have the same sample time setting. (See also Control Ports.)
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