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R2011b Documentation → Simulink HDL Coder
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Contents

Index

• Getting Started

Automated HDL Code Generation in the Hardware Development Process

Summary of Key Features

Software Requirements

Installing the Software

• User's Guide

• Introduction to HDL Code Generation

• Code Generation Options in the Simulink HDL Coder Dialog Boxes

• Specifying Block Implementations and Parameters for HDL Code Generation

• Guide to Supported Blocks and Block Implementations

• Generating HDL Code for Multirate Models

• The hdldemolib Block Library

• Streaming, Resource Sharing, and Delay Balancing

• Generating Bit-True Cycle-Accurate Models

• Code Generation Reports, HDL Compatibility Checker, Block Support Library, and Code Annotation

• Interfacing Subsystems and Models to HDL Code

• Stateflow HDL Code Generation Support

• Generating HDL Code with the MATLAB Function Block

• Generating Scripts for HDL Simulators and Synthesis Tools

• Using the HDL Workflow Advisor

What Is the HDL Workflow Advisor?

• HDL Workflow Advisor Compatibility with Third-Party Tools

Supported Third-Party Synthesis Tools

Setting Up the Synthesis Tool Path

Starting the HDL Workflow Advisor

Using the HDL Workflow Advisor Window

• Selecting and Running HDL Workflow Advisor Tasks

Task Execution Order

Changing the Device Under Test

Selecting and Running Tasks Individually

Selecting and Running a Sequence of Tasks

• Saving and Restoring the HDL Workflow Advisor State

How the Save and Restore Process Works

Limitations of the Save and Restore Process

Saving the HDL Workflow Advisor State

Restoring the HDL Workflow Advisor State

Correcting a Warning or Failure Problem

• Generating HDL Workflow Advisor Reports

Viewing HDL Workflow Advisor Reports

Saving HDL Workflow Advisor Reports

Setting the Target Device and Synthesis Tool

• Performing FPGA Synthesis and Analysis Tasks with Third-Party Tools

FPGA Synthesis and Analysis Tasks Overview

Creating a Synthesis Project

Performing Synthesis, Mapping, and Place and Route

Annotating Your Model with Critical Path Information

• Performing FPGA-in-the-Loop

How FPGA-in-the-Loop Works

Using the HDL Workflow Advisor for FPGA-in-the-Loop

Automated Workflows for Specific Target Devices and Synthesis Tools

• Workflow for Speedgoat FPGA IO Boards and xPC Target

Selecting a Speedgoat Target Device

Setting the Target Interface for Speedgoat Boards

Code Generation, Synthesis, and Generation of xPC Target Interface Subsystem

• Workflow for Xilinx FPGA Development Boards

Selecting the Target Device

Setting the Target Interface

Code Generation, Synthesis, and Programming of Target Device

• HDL Workflow Advisor Tasks

• Code Generation Control Files

• Property Reference

• Release Notes

Using the HDL Workflow Advisor

Custom Script Generation

Custom Script Generation

What Is the HDL Workflow Advisor?

What Is the HDL Workflow Advisor?

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