Overview of Model Verification Blocks

Model verification blocks monitor model signals and model characteristics, and check that they remain within specified bounds during simulation.

Simulink Model Verification library blocks monitor time-domain signals in your model, according to the specifications that you assign to the blocks.

Note   To see a complete description of all Simulink model verification blocks, see the Model Verification category in the Simulink Block Reference documentation.

If you have Simulink Control Design™ software, you can also monitor frequency-domain characteristics such as:

• Gain and phase margins

• Peak magnitude

Note   For more information about the Simulink Control Design model verification blocks, see Model Verification in the Simulink Control Design documentation.

You set a verification block to assert when its signal leaves the limit or range that you specify. During simulation, when the signal crosses the limit, the verification block can:

• Stop the simulation and bring immediate focus to that part of the model.

• Report the limit encounter with a logical signal output of its own. If the simulation does not encounter the limit, the signal output is true. If the simulation encounters the limit, the signal output is false.

Use these blocks with the Verification Manager tool in the Signal Builder to construct simulation tests for your model.

Using Model Verification Blocks

Example: Using the Check Static Lower Bound Block to Check for Out-of-Bounds Signal

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