|
|
|
| R2012a Documentation → xPC Target | |
Learn more about xPC Target |
|
| Contents | Index |
xPC Target Library for MPL
The Freescale MPC555 processor contains two time processor units (TPUs). Each TPU has 16 timer channels (1 to 16 and 17 to 32), totaling 32 channels, for one MPL PATI board. Each TPU has two time bases (four between the two TPUs) that can be used in the timer functions. The basic frequency for the TPU is the clock frequency for the CPU, (40 MHz). The minimum divider that can be applied is a factor of 2, which gives the maximum timer frequency of 20 MHz. This block allows you to set the frequency for each of the four time bases, two time bases for channels 1 to 16 and two for channels 17 to 32.
Each TPU allows two different timer sources called TCR1 and TCR2.
TCR1 is driven by a clock source with a frequency of 40 MHz/N, where N is a power of 2 between 2 and 512.
TCR2 can be driven either by an external clock source or by a clock source with a frequency of 40 MHz/N, where N is a power of 2 between 8 and 32. Note that the MPL PATI user documentation refers to the channel's 17 to 32 external input as TPU_T2CLKB.
The hardware architecture restricts allowable values for the time bases. See the MPC555 documentation from Freescale Semiconductor at http://www.freescale.com for more information on the TPUs and time bases.
Note To execute a model using this block, you must first write MPL boot code on the EEPROM using the MPL PATI EEPROM Write block. To flash the EEPROM with the boot code, add the EEPROM Write block to an empty model, then build and execute that model before executing the actual model. See MPL PATI EEPROM Write block for further information. |
From the list, choose the divider that sets the TCR1 time base for channels 1 to 16. The minimum divider of 2 gives the maximum time base frequency of 20 MHz. The maximum divider of 512 gives a time base frequency of 78.125 kHz.
From the list, choose one of the following:
8 (5 Mhz) or ext
16 (2.5 Mhz) or ext/2
32 (1.25 Mhz) or ext/4
64 (625 Khz) or ext/8
This divider sets the TCR2 time base for channels 1 to 16. You can specify that the TCR2 time base can be driven by either the 40 MHz CPU clock or by a signal on the external T2CLK input pin. Note that the maximum frequency of the external signal is approximately 40 MHz/9 = 4.44 MHz.
If you want to use the external clock, select the TCR2 external clock input (1–16) check box.
Select this check box to use the signal on the T2CLK pin as the source for TCR2. Use this parameter with the TCR2 divider (1–16) parameter.
From the list, choose the divider that sets the TCR1 time base for channels 17 to 32. A minimum divider of 2 gives the maximum time base frequency of 20 MHz. A maximum divider of 512 gives a time base frequency of 78.125 kHz.
From the list, choose one of the following:
8 (5 Mhz) or ext
16 (2.5 Mhz) or ext/2
32 (1.25 Mhz) or ext/4
64 (625 Khz) or ext/8
This divider sets the TCR2 time base for channels 1 to 16. You can specify that the TCR2 time base can be driven by either the 40 MHz CPU clock or by a signal on the external T2CLK input pin. Note that the maximum frequency of the external signal is approximately 40 MHz/9 = 4.44 MHz.
If you want to use the external clock, select the TCR2 external clock input (17–32) check box.
Select this check box to use the signal on the T2CLK pin as the source for TCR2. Use this parameter with the TCR2 divider (17–32) parameter.
If only one board of this type is in the target PC, enter
-1
to automatically locate the board.
If two or more boards of this type are in the target PC, enter the bus number and the PCI slot number of the board associated with this driver block. Use the format [BusNumber, SlotNumber]. To determine the bus number and the PCI slot number, type
getxpcpci
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
| © 1984-2012- The MathWorks, Inc. - Site Help - Patents - Trademarks - Privacy Policy - Preventing Piracy - RSS |
