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Speedgoat IO313 PCI Read

Speedgoat IO313 PCI Read block

Description

The Speedgoat IO313 PCI Read block reads a 32–bit data value from a PCI port offset address. Output is a uint32 data type.

The Speedgoat FPGA I/O board block descriptions are for informational purposes only. The HDL Coder™ HDL Workflow Advisor uses these blocks to generate a Simulink® Real-Time™ interface subsystem. The subsystem mask controls the block parameters. Do not edit the parameters directly.

Library

Simulink Real-Time Library for FPGA

Block Parameters

Device index

Enter a number between 0 and 7. The maximum number of allowed boards is 8.

Port name

Enter the FPGA output port name.

Port offset

Enter the PCI register offset address for the ports being read.

Valid offset addresses begin at 0x8000. Each PCI address must be unique and 32-bit aligned, such as hex2dec('8000'), hex2dec('8004'), and so on.

Port type

Enter the data type of the ports being read (uint32 (fixed)).

Port dimension

Enter the dimension of the ports being read (number of addresses to read). If Port dimension is greater than 1, you must use a strobe.

Strobe offset

Enter the PCI register offset address for the signal being used to latch data from the FPGA into the ports being read. If Strobe offset is 0, the strobe is not used.

Valid offset addresses begin at 0x8000. Each PCI address must be unique and 32-bit aligned, such as hex2dec('8000'), hex2dec('8004'), and so on.

Sample time

Enter the base sample time or a multiple of the base sample time (-1 means sample time is inherited).

Related Examples

External Websites

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