How to Configure "use ieee.std_logic_unsigned.all; " in HDL Coder
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Ashish Kumar
on 15 Mar 2015
Answered: Tim McBrayer
on 16 Mar 2015
Is it possible to configure HDL Coder to generate VHDL code using "use ieee.std_logic_unsigned.all; " package ?
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Tim McBrayer
on 16 Mar 2015
The use of std_logic_unsigned, while convenient, is not supported by HDL Coder. Many people in the industry feel the use of the std_logic_unsigned and std_logic_signed packages can lead to a lack of clarity in VHDL code. The explicit use of the signed, unsigned, and std_logic types is a code style that leads to an unambiguous definition of each signal's type and an indication of what operations are permitted. This style is what is supported by HDL Coder.
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