why HDL coder behaves differently for "HDL counter"?

I create simulink module which contains the block "HDL Counter" from hdlsllib library;

then generate HDL file by HDL code; the hdl code sytyle is very nice; following is the code:

======================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY CNTER IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        EN                                :   IN    std_logic;
        O_CNT                             :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
        );
END CNTER;

ARCHITECTURE rtl OF CNTER IS

    -- Signals
    SIGNAL HDL_Counter_out1                 : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL HDL_Counter_stepreg              : unsigned(7 DOWNTO 0);  -- uint8
  BEGIN
    -- Count limited, Unsigned Counter
    --  initial value   = 0
    --  step value      = 1
    --  count to value  = 25
    HDL_Counter_step_process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        HDL_Counter_stepreg <= to_unsigned(16#01#, 8);
      ELSIF clk'EVENT AND clk = '1' THEN
        IF EN = '1' THEN
          IF HDL_Counter_out1 = to_unsigned(16#18#, 8) THEN
            HDL_Counter_stepreg <= to_unsigned(16#E7#, 8);
          ELSE
            HDL_Counter_stepreg <= to_unsigned(16#01#, 8);
          END IF;
        END IF;
      END IF;
    END PROCESS HDL_Counter_step_process;

    HDL_Counter_process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        HDL_Counter_out1 <= to_unsigned(16#00#, 8);
      ELSIF clk'EVENT AND clk = '1' THEN
        IF EN = '1' THEN
          HDL_Counter_out1 <= HDL_Counter_out1 + HDL_Counter_stepreg;
        END IF;
      END IF;
    END PROCESS HDL_Counter_process;

    O_CNT <= std_logic_vector(HDL_Counter_out1);

END rtl;

=========================================================

but when I disable library link for the block "HDL Counter", and re-generate HDL again;

I find the style of HDL file is very poor; such as:

=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY HDL_Counter IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb_1                             :   IN    std_logic;
        count                             :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
        );
END HDL_Counter;

ARCHITECTURE rtl OF HDL_Counter IS
  -- Component Declarations
  COMPONENT Dir_logic
    PORT( dir_port                        :   IN    std_logic;
          dn                              :   OUT   std_logic
          );
  END COMPONENT;

    COMPONENT Sub_wrap
      PORT( step                            :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
            fb                              :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
            sub                             :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
            );
    END COMPONENT;

    COMPONENT Add_wrap
      PORT( step                            :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
            fb                              :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
            add                             :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
            );
    END COMPONENT;

    -- Component Configuration Statements
    FOR ALL : Dir_logic
      USE ENTITY work.Dir_logic(rtl);

    FOR ALL : Sub_wrap
      USE ENTITY work.Sub_wrap(rtl);

    FOR ALL : Add_wrap
      USE ENTITY work.Add_wrap(rtl);
    -- Signals
    SIGNAL const_load_out1                  : std_logic;
    SIGNAL Free_running_out1                : std_logic;
    SIGNAL const_dir_out1                   : std_logic;
    SIGNAL Dir_logic_out1                   : std_logic;
    SIGNAL Step_value_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL From_value_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL const_rst_out1                   : std_logic;
    SIGNAL const_load_val_out1              : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Init_value_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Count_reg_out1                   : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Sub_wrap_out1                    : std_logic_vector(7 DOWNTO 0);  -- ufix8
    SIGNAL Sub_wrap_out1_unsigned           : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Add_wrap_out1                    : std_logic_vector(7 DOWNTO 0);  -- ufix8
    SIGNAL Add_wrap_out1_unsigned           : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Switch_dir_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Max_value_out1                   : std_logic;
    SIGNAL Switch_max_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Switch_type_out1                 : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Switch_enb_out1                  : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Switch_load_out1                 : unsigned(7 DOWNTO 0);  -- uint8
    SIGNAL Switch_reset_out1                : unsigned(7 DOWNTO 0);  -- uint8
  BEGIN
    u_Dir_logic : Dir_logic
      PORT MAP( dir_port => const_dir_out1,
                dn => Dir_logic_out1
                );

    u_Sub_wrap : Sub_wrap
      PORT MAP( step => std_logic_vector(Step_value_out1),  -- uint8
                fb => std_logic_vector(Count_reg_out1),  -- uint8
                sub => Sub_wrap_out1  -- uint8
                );

    u_Add_wrap : Add_wrap
      PORT MAP( step => std_logic_vector(Step_value_out1),  -- uint8
                fb => std_logic_vector(Count_reg_out1),  -- uint8
                add => Add_wrap_out1  -- uint8
                );

    const_load_out1 <= '0';

    Free_running_out1 <= '0';

    const_dir_out1 <= '1';

    Step_value_out1 <= to_unsigned(16#01#, 8);

    From_value_out1 <= to_unsigned(16#00#, 8);

    const_rst_out1 <= '0';

    const_load_val_out1 <= to_unsigned(16#00#, 8);

    Init_value_out1 <= to_unsigned(16#00#, 8);

    Sub_wrap_out1_unsigned <= unsigned(Sub_wrap_out1);

    Add_wrap_out1_unsigned <= unsigned(Add_wrap_out1);

    Switch_dir_out1 <= Add_wrap_out1_unsigned WHEN Dir_logic_out1 = '0' ELSE
        Sub_wrap_out1_unsigned;

    Max_value_out1 <= '1' WHEN Count_reg_out1 = to_unsigned(16#19#, 8) ELSE
        '0';

    Switch_max_out1 <= Switch_dir_out1 WHEN Max_value_out1 = '0' ELSE
        From_value_out1;

    Switch_type_out1 <= Switch_max_out1 WHEN Free_running_out1 = '0' ELSE
        Switch_dir_out1;

    Switch_enb_out1 <= Count_reg_out1 WHEN enb_1 = '0' ELSE
        Switch_type_out1;

    Switch_load_out1 <= Switch_enb_out1 WHEN const_load_out1 = '0' ELSE
        const_load_val_out1;
    Switch_reset_out1 <= Switch_load_out1 WHEN const_rst_out1 = '0' ELSE
        Init_value_out1;

    Count_reg_process : PROCESS (clk, reset)
    BEGIN
      IF reset = '1' THEN
        Count_reg_out1 <= to_unsigned(16#00#, 8);
      ELSIF clk'EVENT AND clk = '1' THEN
        Count_reg_out1 <= Switch_reset_out1;
      END IF;
    END PROCESS Count_reg_process;

    count <= std_logic_vector(Count_reg_out1);

END rtl;

=============================================

could any body explain why this happened? how to control the HDL code style generated by HDL coder?

Answer 1

[Tim McBrayer]

When HDL Coder has a linked library block for the HDL Counter (or any other block supplied with the tool), it can recognize the semantic behavior for the block and emit optimized code specific to the block's behavior. In this case since HDL Coder knows the block is a "HDL Counter" it emits the optimized "HDL Counter" code.

When you break the library link, you are removing the semantic information that this block is a MathWorks-supplied "HDL Counter". In this case HDL Coder only has the underlying Simulink blocks (that define the Simulink simulation semantics) to use to implement the block in HDL. So, with the library link broken HDL Coder generates code for each block under the mask individually, just as it would do with a user-defined Subsystem.

Both implementations are bit-true and cycle-accurate to the Simulink simulation behavior. But, as you have observed, it is difficult to make a collection of independent Simulink blocks generate code that is as readable as an implementation working at a higher level of abstraction.