Generate model from existing vhdl entity
1 view (last 30 days)
Show older comments
I have a question regarding HDL Coder which we are evaluating right now. How can I set up an model from an existing VHDL entity. The interface should be created automatically from the architecture. Tried to find that in the docs, but could not find a solution to that.
0 Comments
Answers (2)
Tim McBrayer
on 20 Dec 2011
The ability to do this automatically is not currently part of Simulink HDL Coder. It can be done manually, though, by building a subsystem with the desired IO interface as part of your larger HDL model. You should choose "BlackBox" for the HDL Block Architecture property. Simulink HDL Coder will generate a component instantiation using the names, ports, data widths, and so forth, from the BlackBox subsystem, integrated into your larger code generation model. It will not generate any code for the contents of that subsystem.
0 Comments
See Also
Categories
Find more on HDL Coder in Help Center and File Exchange
Products
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!