Question related to HDL verifier

Hi, I am using HDL verifier to test my hand written code for Cyclone V FPGA. This code was written in Quartus II. I use FIL wizard to include it in my simulink model file. I setup FIL wizard properly and build the code and it takes about 1 hour and 22 minutes and sometimes more to fit, place, route and generate programming file. I cannot understand the reason behind this. Moreover, I have observed that when I separately compile my code using Quartus II software. The fitting,placement and routing and generating programming file process finishes within 5-10 minutes. Kindly help me to solve this issue because it is delaying my development process. Thanks for your help!

Answer 1

[Laszlo Huber]

Kindly reply.