I can't get black boxes in system generator to output more than 1 bit. Help!

Hi,

I've been stuck on this for days,so I would really appreciate some input. I have VHDL code that I have dropped into a SysGen design as black boxes. If the output is 1 bit (either cast as a boolean or as uFix1_0, it outputs correctly. If it is any more than that it only outputs 0 across all bits. If I decompose a signal into individual bits it works fine.

I'm running Matlab2015b with SysGen 2015.4 on Windows 7. Below is an example config.m file

function BankGenerator_config(this_block)

    % Revision History:
    %
    %   14-Dec-2015  (13:40 hours):
    %     Original code was machine generated by Xilinx's System Generator after parsing
    %     C:\Users\hal346\ACM\Sysgen\ACM_192x192_quarter\BankGenerator.vhd
    %
    %

    this_block.setTopLevelLanguage('VHDL');

    this_block.setEntityName('BankGenerator');

    % System Generator has to assume that your entity  has a combinational feed through; 
    %   if it  doesn't, then comment out the following line:
    this_block.tagAsCombinational;

    this_block.addSimulinkInport('Fin');
    this_block.addSimulinkInport('Sin');

    this_block.addSimulinkOutport('bank');
    this_block.addSimulinkOutport('bankChange');
    this_block.addSimulinkOutport('sample');

    bank_port = this_block.port('bank');
    bank_port.setType('UFix_1_0');
    bank_port.useHDLVector(false);
    bankChange_port = this_block.port('bankChange');
    bankChange_port.setType('UFix_1_0');
    bankChange_port.useHDLVector(false);
    sample_port = this_block.port('sample');
    sample_port.setType('UFix_2_0');

    % -----------------------------
    if (this_block.inputTypesKnown)
      % do input type checking, dynamic output type and generic setup in this code block.

      if (this_block.port('Fin').width ~= 1);
        this_block.setError('Input data type for port "Fin" must have width=1.');
      end

      this_block.port('Fin').useHDLVector(false);

      if (this_block.port('Sin').width ~= 1);
        this_block.setError('Input data type for port "Sin" must have width=1.');
      end

      this_block.port('Sin').useHDLVector(false);

    end  % if(inputTypesKnown)
    % -----------------------------

    % -----------------------------
     if (this_block.inputRatesKnown)
       setup_as_single_rate(this_block,'clk','ce')
     end  % if(inputRatesKnown)
    % -----------------------------

      uniqueInputRates = unique(this_block.getInputRates);

    % Add addtional source files as needed.
    %  |-------------
    %  | Add files in the order in which they should be compiled.
    %  | If two files "a.vhd" and "b.vhd" contain the entities
    %  | entity_a and entity_b, and entity_a contains a
    %  | component of type entity_b, the correct sequence of
    %  | addFile() calls would be:
    %  |    this_block.addFile('b.vhd');
    %  |    this_block.addFile('a.vhd');
    %  |-------------

    %    this_block.addFile('');
    %    this_block.addFile('');
    this_block.addFile('BankGenerator.vhd');

return;

% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.addError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.addError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------

Thanks for your help

[Yongfeng]

You'd better ask Xilinx about this.