Using unit delay with HDL Code Generator

Hello! I'm trying generate HDL code for next block, which calculates derivative of input signal with Sample Time = 200 us.

 How I can provide it for FPGA with clock 100 MHz (clock period 10 ns)? I must delay signal in "Delay" block for one sample time = 200 us, but I have delay for one period of clock = 10 ns.