I'd like to be able to specify an input port to output port dependency on my mex function Simulink blocks to that Simulink doesn't falsely think there are algebraic loops. Is this possible? Could it be made possible?
For example, for some of my blocks there's a simple input to output port relationship (output port N is dependent only on input port N), If any output port loops back without a delay (e.g. output port M loops back through combinational logic to input port P, ( P != M)), Simulink will think this is an algebraic loop, as it will assume all input ports to the block drive all outputs (for this example that there is a connection from P to M in the block). I want to tell Simulink there is no such connection and therefore no loop by specifying some internal connectivity relationship for my block.