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Insert algorithms on Verilog language to Simulink

Asked by Yuriy on 15 Apr 2013

How to insert algorithms on Verilog language to Simulink?

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Yuriy

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1 Answer

Answer by Tim McBrayer on 15 Apr 2013
Accepted answer

If you have HDL Verifier, you can cosimulate your design with Simulink using either Cadence Incisive or Mentor Graphics ModelSim. You will of course need one or the other of the HDL simulators.

The high-level overview is that you create a HDL cosimulation block in Simulink that has the same interface as your top-level Verilog code. Simulink then executes its simulation, calling the HDL simulator each time the cosimulation block is scheduled to execute.

2 Comments

Yuriy on 16 Apr 2013

How I can cosimulate my design with Simulink using "Synopsys" software?

Tim McBrayer on 16 Apr 2013

The latest versions of HDL Verifier do not support Synopsys simulators. There are some past versions that have supported integration with Synopsys simulators. Your only chance here would be to find a compatible pair of MathWorks and Synopsys tools. Neither tool would be very recent, unfortunately.

Tim McBrayer

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