If you have HDL Verifier, you can cosimulate your design with Simulink using either Cadence Incisive or Mentor Graphics ModelSim. You will of course need one or the other of the HDL simulators.
The high-level overview is that you create a HDL cosimulation block in Simulink that has the same interface as your top-level Verilog code. Simulink then executes its simulation, calling the HDL simulator each time the cosimulation block is scheduled to execute.
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