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sampling rate error in fpga design of brushless dc motor

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vikas
vikas on 27 Apr 2013
Closed: Sabin on 19 Dec 2022
i have designed fpga based speed control model of brushless dc motor in simulink. the controlling blocks used are from xilinx blocksets. and the pid controller is from DMC library. When I run the model I got the error that
*The periodic sample time 1000000.0 is not allowed because the ratio of this sample time over base rate (1.0E-6) is greater than the maximum value of uint32.*
plz help me

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