This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
If you're interested in this submission, you might also like the new, free mixed-signal library available from here: http://www.mathworks.com/programs/mixed-signal/index.html
??? Error using ==> construct_error at 109
DOS commands may not be executed when the current
directory is a UNC pathname
Please change the current directory to a local directory
or use a network drive mapped to the current directory.
Warning: Unable to load block diagram 'powerlib'
> In plldemo at 181
??? Error using ==> plldemo at 181
Failed to load library 'powerlib' referenced by
'powerpll/Charge Pump Loop Filter/+10V'.
Caused by:
Error using ==> plldemo at 181
Unable to open file for reading: "powerlib.mdl".
You can plot the two curves on one axis using a Mux (in Signal Routing). Run the Mux output to the scope and you'll be able to see the offset more clearly.
cp_pll has run time error
"Error reported by S-function 'scominhshape' in cppll/Continous time VCO/Inherit Shape1"
Input and output frame status or dimension are invalid.
?
Also how to plot the 2 input scope on top of each other so I can see the phase offset?