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Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

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Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

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17 Sep 2007 (Updated )

Model-Based Design of a Sigma-Delta ADC, from behavioral model to VHDL code.

sigma_delta_control
function c = sigma_delta_control

c = hdlnewcontrol(mfilename);

c.forEach('design_multi_stage3/Stage1_40_Tap_FIR_using_LUT/Sum',...
 'built-in/Sum', {},...
 'hdldefaults.ProductTreeHDLEmission',{});

%for tree implementation use hdldefaults.ProductTreeHDLEmission
%for cascade implementaiton use hdldefaults.ProductCascadeHDLEmission

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