Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL: sigma_delta_control - File Exchange

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Highlights from
Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

sigma_delta_control for tree implementation use hdldefaults.ProductTreeHDLEmission
y=bin2sbin(x)
filter_design.m
generate_fir_lut.m
elaborated_design
fixed_point
high_level
multi_stage
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from Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL by Ali Behboodian
Model-Based Design of a Sigma-Delta ADC, from behavioral model to VHDL code.

sigma_delta_control

function c = sigma_delta_control

c = hdlnewcontrol(mfilename);

c.forEach('design_multi_stage3/Stage1_40_Tap_FIR_using_LUT/Sum',...
 'built-in/Sum', {},...
 'hdldefaults.ProductTreeHDLEmission',{});

%for tree implementation use hdldefaults.ProductTreeHDLEmission
%for cascade implementaiton use hdldefaults.ProductCascadeHDLEmission

Highlights from Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL

Highlights from
Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL